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1. 发明授权

US08520740B2 Arithmetic decoding acceleration 失效
标题翻译：算术解码加速
公开(公告)号：US08520740B2
公开(公告)日：2013-08-27
申请号：US12874564
申请日：2010-09-02
申请人： Brian Flachs , Charles R. Johns , Michael A. Kutner , Brad W. Michael , Naxin Wang
发明人： Brian Flachs , Charles R. Johns , Michael A. Kutner , Brad W. Michael , Naxin Wang
IPC分类号： H04N7/12
CPC分类号： H04N19/436 , H04N19/13 , H04N19/44 , H04N19/91
摘要： Mechanisms for performing decoding of context-adaptive binary arithmetic coding (CABAC) encoded data. The mechanisms receive, in a first single instruction multiple data (SIMD) vector register of the data processing system, CABAC encoded data of a bit stream. The CABAC encoded data includes a value to be decoded and bit stream state information. The mechanisms receive, in a second SIMD vector register of the data processing system, CABAC decoder context information. The mechanisms process the value, the bit stream state information, and the CABAC decoder context information in a non-recursive manner to generate a decoded value, updated bit stream state information, and updated CABAC decoder context information. The mechanisms store, in a third SIMD vector register, a result vector that combines the decoded value, updated bit stream state information, and updated CABAC decoder context information. The mechanisms use the decoded value to generate a video output on the data processing system.
摘要翻译：用于执行上下文自适应二进制算术编码（CABAC）编码数据的解码的机制。这些机制在数据处理系统的第一个单指令多数据（SIMD）向量寄存器中接收位数据流的CABAC编码数据。 CABAC编码数据包括要解码的值和位流状态信息。该机制在数据处理系统的第二SIMD向量寄存器中接收CABAC解码器上下文信息。该机制以非递归方式处理值，比特流状态信息和CABAC解码器上下文信息，以生成解码值，更新的比特流状态信息和更新的CABAC解码器上下文信息。该机制在第三SIMD向量寄存器中存储组合解码值，更新位流状态信息和更新的CABAC解码器上下文信息的结果向量。这些机制使用解码的值在数据处理系统上生成视频输出。

2. 发明申请

US20110310972A1 SYSTEM AND METHOD FOR GENERATING DECODED DIGITAL VIDEO IMAGE DATA 审中-公开
标题翻译：用于生成解码的数字视频图像数据的系统和方法
公开(公告)号：US20110310972A1
公开(公告)日：2011-12-22
申请号：US13217806
申请日：2011-08-25
申请人： Jason Naxin Wang , Ikuo Tsukagoshi
发明人： Jason Naxin Wang , Ikuo Tsukagoshi
IPC分类号： H04N7/50 , H04N7/26 , H04N7/30
CPC分类号： H04N19/59 , H04N19/122 , H04N19/132 , H04N19/134 , H04N19/159 , H04N19/176 , H04N19/18 , H04N19/44 , H04N19/523 , H04N19/61
摘要： Methods and systems are disclosed for decoding image data including I-picture, P-picture, and B-picture encoded data. A method includes receiving encoded image data and selectively performing a modified inverse discrete cosine transform (IDCT) process to generate output pixel array blocks at a lower resolution than the resolution of the received image data. The image data can be 8×8 pixel array blocks, which are used to produce lower resolution pixel array blocks such as, for example, 4×8 or 4×4 pixel array blocks. In certain instances, after the IDCT process is performed, the resulting pixel data is up-sampled before motion compensation is performed. Furthermore, in certain instances, the resulting pixel data is subjected to motion compensation and scaled to display size prior to display.
摘要翻译：公开了用于对包括I图像，P图像和B图像编码数据的图像数据进行解码的方法和系统。一种方法包括接收编码图像数据并选择性地执行修改的反相离散余弦变换（IDCT）处理，以以比接收到的图像数据的分辨率低的分辨率生成输出像素阵列块。图像数据可以是8×8像素阵列块，其用于产生较低分辨率像素阵列块，例如4×8或4×4像素阵列块。在某些情况下，在执行IDCT处理之后，在执行运动补偿之前对所得到的像素数据进行上采样。此外，在某些情况下，对所得像素数据进行运动补偿并在显示之前缩放以显示尺寸。

3. 发明授权

US06317767B2 Methods and systems for performing short integer chen IDCT algorithm with fused multiply/add 有权
公开(公告)号：US06317767B2
公开(公告)日：2001-11-13
申请号：US09828231
申请日：2001-04-09
申请人： Naxin Wang
发明人： Naxin Wang
IPC分类号： G06F1714
CPC分类号： G06F17/147
摘要： Methods and apparatus for performing a fast two-dimensional inverse discrete cosine transform (IDCT) in a media processor are disclosed. A processor receives discrete cosine transform data and combines, in a first stage, the discrete cosine transform data with a first set of constants. In a media processor with a partitioned SIMD architecture, the discrete cosine transform data and first set of constants may be combined, for example, by multiplying the at least one input component with a first set of constants using a complex multiplication instruction. The output is transposed in a second stage and combined with constants in a third stage to obtain the pixel information of an image.

4. 发明申请

US20090100188A1 METHOD AND SYSTEM FOR CLUSTER-WIDE PREDICTIVE AND SELECTIVE CACHING IN SCALABLE IPTV SYSTEMS 审中-公开
标题翻译：用于可扩展IPTV系统中的群集预测和选择性高速缓存的方法和系统
公开(公告)号：US20090100188A1
公开(公告)日：2009-04-16
申请号：US11870563
申请日：2007-10-11
申请人： Qiang Li , Naxin Wang , Li-Cheng Tai , Zhen Zeng
发明人： Qiang Li , Naxin Wang , Li-Cheng Tai , Zhen Zeng
IPC分类号： G06F15/16
CPC分类号： H04N21/6125 , H04L65/4076 , H04L67/2852 , H04N21/23106 , H04N21/2393 , H04N21/2405 , H04N21/26283 , H04N21/4331 , H04N21/47202 , H04N21/8456
摘要： A method for caching of stream data is accomplished by assigning for each video segment in the system a likelihood rating of future showing and then determining for each node that contains a copy of the segment a second likelihood value that reflecting a probability that the node will be used to serve streams for the segment. The future cost value of a segment copy is then predicted and preload orders are issued to nodes for segments with the per-copy likelihood above a predefined threshold.
摘要翻译：用于缓存流数据的方法是通过为系统中的每个视频段分配未来显示的可能性等级，然后为包含该段的副本的每个节点确定第二似然值来反映该节点将被用于为细分市场提供流。然后预测片段副本的未来成本值，并且将预加载顺序发布给每个副本可能性高于预定义阈值的段的节点。

5. 发明申请

US20090019493A1 CACHE AFFILIATION IN IPTV EPG SERVER CLUSTERING 审中-公开
标题翻译： IPTV EPG服务器群集中的高速缓存处理
公开(公告)号：US20090019493A1
公开(公告)日：2009-01-15
申请号：US11776947
申请日：2007-07-12
申请人： Qiang Li , Chen Ma , Huiyou Zhu , Naxin Wang
发明人： Qiang Li , Chen Ma , Huiyou Zhu , Naxin Wang
IPC分类号： H04N5/445
CPC分类号： H04N7/17336 , H04N21/23116 , H04N21/2393 , H04N21/84
摘要： An EPG service architecture incorporates multiple EPG servers connected in a cluster. An active dispatcher is associated with at least one EPG server and multiple standby dispatchers are associated with the cluster. A plurality of STBs interfaced with the EPG server cluster issue requests for EPG service for which the active dispatcher employs an affiliation table as a portion of the cache for redirecting each request to a specific one of the EPG servers affiliated with the STB issuing the request. The active dispatcher multicasts the affiliation table to the multiple standby dispatchers for synchronization.
摘要翻译： EPG服务架构集成了多个连接在集群中的EPG服务器。主动调度器与至少一个EPG服务器相关联，并且多个备用调度器与集群相关联。与EPG服务器集群接口的多个STB发出对EPG服务的请求，活动调度员使用附属表作为缓存的一部分，将每个请求重定向到与发出请求的STB相关联的EPG服务器的特定一个。活动分派器将附属表组播到多个备用分派器进行同步。

6. 发明申请

US20080005349A1 DISTRIBUTED MULTIMEDIA STREAMING SYSTEM 审中-公开
标题翻译：分布式多媒体流媒体系统
公开(公告)号：US20080005349A1
公开(公告)日：2008-01-03
申请号：US11744924
申请日：2007-05-07
申请人： Qiang Li , Jifei Song , Zhen Zeng , Naxin Wang
发明人： Qiang Li , Jifei Song , Zhen Zeng , Naxin Wang
IPC分类号： G06F15/16
CPC分类号： H04L65/4076 , H04L12/1859 , H04L67/1002 , H04L67/1008 , H04L67/101 , H04L67/1021 , H04L67/1023
摘要： A media content distribution system for distributed multimedia streaming communicates over a network and incorporates multiple independent media stations, each having a media director for control and a number of media engines for storage, retrieval and streaming of media content. A content request from a media console connected to the network is redirected by the media director to a selected one of the media engines storing content corresponding to the request for streaming. Statistical indicators are defined for measuring effectiveness of the content distribution network. Push and pull indicators with additional differentiation for remote and local access to pulled content provide means for efficiency determination of data distribution and storage. A middleware Application Programming Interface (API) structure is provided for flexible interfacing between media consoles and content distribution system components.
摘要翻译：用于分布式多媒体流的媒体内容分发系统通过网络进行通信，并且包括多个独立媒体站，每个独立媒体站具有用于控制的媒体导向器和用于媒体内容的存储，检索和流媒体的多个媒体引擎。来自连接到网络的媒体控制台的内容请求被媒体主管重定向到存储与流请求请求相对应的内容的所选媒体引擎之一。统计指标用于衡量内容分发网络的有效性。推拉指标，具有远程和本地访问拉动内容的其他差异，为数据分配和存储的效率确定提供了手段。提供了中间件应用编程接口（API）结构，用于媒体控制台和内容分发系统组件之间的灵活接口。

7. 发明申请

US20070101012A1 METHOD AND APPARATUS FOR AUTOMATIC SWITCHING OF MULTICAST/UNICAST LIVE TV STREAMING IN A TV-OVER-IP ENVIRONMENT 失效
标题翻译：电视转播环境下多媒体/电视直播电视频道自动切换的方法与装置
公开(公告)号：US20070101012A1
公开(公告)日：2007-05-03
申请号：US11163790
申请日：2005-10-31
申请人： Qiang Li , Naxin Wang , Li-Cheng Tai
发明人： Qiang Li , Naxin Wang , Li-Cheng Tai
IPC分类号： G06F15/16
CPC分类号： H04L29/06027 , H04L65/4092 , H04L65/605 , H04L65/608
摘要： A system for live TV transmission over IP networks incorporates a content encoder receiving live TV broadcast and converting to RTP packets for multicast streaming. A streaming server receives the multicast RTP packets from the content encoder and converts the multicast stream to a unicast stream. The streaming server is also responsive to RTSP commands for trick mode operation. A settop box is connected through an IP network for receiving multicast RTP packets from the content encoder and generating RTSP commands for trick mode operation, the setup box issuing a leave multicast group signal upon issuing a trick mode command and receiving unicast transmission of RTP packets from the streaming server controllable by the trick mode commands.
摘要翻译：用于通过IP网络实时电视传输的系统包括内容编码器，其接收直播电视广播并转换为用于组播流的RTP分组。流服务器从内容编码器接收多播RTP分组，并将多播流转换为单播流。流服务器还响应于RTSP命令进行特技模式操作。机顶盒通过IP网络连接，用于从内容编码器接收多播RTP分组，并产生用于特技模式操作的RTSP命令，该设置框在发出特技模式命令时发出离开组播组信号，并接收来自流服务器可以通过特技模式命令控制。

8. 发明授权

US07142603B2 Method and system for predictive table look-up code length of variable length code 有权
标题翻译：可变长度代码的预测表查找代码长度的方法和系统
公开(公告)号：US07142603B2
公开(公告)日：2006-11-28
申请号：US09933599
申请日：2001-08-20
申请人： Amelia C. Luna , Jason (Naxin) Wang
发明人： Amelia C. Luna , Jason (Naxin) Wang
IPC分类号： H04N7/12
CPC分类号： H03M7/42 , H04N19/60 , H04N19/91
摘要： A method and system for decoding symbols of variable length in a digital video bit stream in real time, using Very Long Instruction Word (VLIW) architecture. In one embodiment, several bit sections are first read from a bit stream. While the first bit section will correspond to a valid symbol in the bit-stream, the rest of the bit sections may or may not, depending on the length of the first section. A table of variable length codes is then indexed to obtain a look-up result for each of the read-in bit sections, which done in parallel for all sections. Next, a determination is made as to whether each of the look-up results is valid. A valid look-up result provides the length of the symbol. The valid look-up values are then accepted. In another embodiment the bit stream is thereafter advanced by the sum of all accepted look-up results.
摘要翻译：一种使用超长指令字（VLIW）架构实时解码数字视频比特流中可变长度符号的方法和系统。在一个实施例中，首先从比特流读取几个比特部分。虽然第一比特部分将对应于比特流中的有效符号，但是其余的比特部分可以或可以不依赖于第一部分的长度。然后对可变长度代码表进行索引，以获得每个读入位部分的查找结果，这些部分对于所有部分并行完成。接下来，确定每个查找结果是否有效。有效的查询结果提供了符号的长度。然后接受有效的查询值。在另一个实施例中，位流随后被所有接受的查找结果的总和推进。

9. 发明授权

US06298087B1 System and method for decoding a variable length code digital signal 有权
标题翻译：用于解码可变长度码数字信号的系统和方法
公开(公告)号：US06298087B1
公开(公告)日：2001-10-02
申请号：US09144693
申请日：1998-08-31
申请人： Amelia Carino Luna , Jason (Naxin) Wang , Richard Lawrence Williams
发明人： Amelia Carino Luna , Jason (Naxin) Wang , Richard Lawrence Williams
IPC分类号： H04N712
CPC分类号： H04N19/91 , H04N19/61
摘要： A variable length code decoder includes modified VLC decode tables as compared to table b.14 and b.15 of Annex B of the ISO/IEC 31818-2 standard, and improved program code for inverse quantising block DCT coefficients. The modified VLC decoding tables include level values corresponding to VLC coded words that have been pre-multiplied by the value 2, or by 2 then plus 1. As a result, the modified tables of the present invention reduces the computational complexity of the inverse quantization calculation of the method of the present invention as compared to the algorithm provided in ISO/IEC 31818-2, section 7. Advantageously, the bandwidth requirement of the inverse quantiser processor is reduced as compared to the bandwidth requirement of an inverse processor executing the inverse quantization calculation as defined in the Standard. Conveniently, lower cost, and more widely available processors may be used in the decoder of the present invention.
摘要翻译：与ISO / IEC 31818-2标准的附件B的表b.14和b.15相比，可变长度码解码器包括修改的VLC解码表，以及用于逆量化块DCT系数的改进的程序代码。经修改的VLC解码表包括对应于已经被乘以值2的VLC编码字或者2乘以1的等级值。结果，本发明的修改表降低了反量化的计算复杂度计算与ISO / IEC 31818-2第7节中提供的算法相比较的本发明方法。有利的是，与执行逆的处理器的逆处理器的带宽要求相比，反量化器处理器的带宽要求降低标准中定义的量化计算。方便地，可以在本发明的解码器中使用较低成本和更广泛可用的处理器。

10. 发明授权

US08437404B2 Implementation of a DV video decoder with a VLIW processor and a variable length decoding unit 有权
标题翻译：具有VLIW处理器和可变长度解码单元的DV视频解码器的实现
公开(公告)号：US08437404B2
公开(公告)日：2013-05-07
申请号：US11594462
申请日：2006-11-07
申请人： Amelia C. Luna , Jason (Naxin) Wang
发明人： Amelia C. Luna , Jason (Naxin) Wang
IPC分类号： H04N11/02
CPC分类号： H04N7/26106 , H04N19/42 , H04N19/60 , H04N19/70 , H04N19/91
摘要： A decoder for decoding a plurality of digital video data is described. In an embodiment, the decoder comprises a DV video decoder for decoding digital video data which is formatted according to the DV standard. The DV video decoder has a Very-Long Instruction Word (VLIW) processor and a variable length decoding unit. The VLIW processor includes a preparser unit for recovering a decoding order of the digital video data so that the variable length decoding unit can process the digital video data. The variable length decoding unit decodes a variable length coding format of the digital video data which has been preparsed by the VLIW processor. Furthermore, the VLIW processor includes a decompression unit for decompressing the digital video data which has been decoded by the variable length decoding unit. In an embodiment, the VLIW processor and the variable length decoding unit are formed on the same semiconductor device.
摘要翻译：描述用于解码多个数字视频数据的解码器。在一个实施例中，解码器包括用于解码根据DV标准格式化的数字视频数据的DV视频解码器。 DV视频解码器具有超长指令字（VLIW）处理器和可变长度解码单元。 VLIW处理器包括用于恢复数字视频数据的解码顺序的准备单元，使得可变长度解码单元可以处理数字视频数据。可变长度解码单元解码由VLIW处理器预先准备的数字视频数据的可变长度编码格式。此外，VLIW处理器包括用于解压缩由可变长度解码单元解码的数字视频数据的解压缩单元。在一个实施例中，VLIW处理器和可变长度解码单元形成在相同的半导体器件上。

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