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1. 发明申请

US20120313173A1 METHOD FOR ISOLATING RF FUNCTIONAL BLOCKS ON SILICON-ON-INSULATOR (SOI) SUBSTRATES 审中-公开
标题翻译：硅绝缘体（SOI）衬底上隔离RF功能块的方法
公开(公告)号：US20120313173A1
公开(公告)日：2012-12-13
申请号：US13490771
申请日：2012-06-07
申请人： Carl Dickey , Nathaniel Peachey , Robert Deuchars
发明人： Carl Dickey , Nathaniel Peachey , Robert Deuchars
IPC分类号： H01L27/12
CPC分类号： H01L27/1203
摘要： Buried implants are used to reduce RF (radio-frequency) coupling in a SOI (Silicon-on-insulator) circuit. These buried implants are located above and/or below the BOX (buried oxide) layer of the SOI circuit. These buried implants may completely enclose the PWELL (P-type well) of an NFET (N-type Field Effect Transistor).
摘要翻译：掩埋式植入物用于降低SOI（绝缘体上硅）电路中的RF（射频）耦合。这些埋入式植入物位于SOI电路的BOX（掩埋氧化物）层的上方和/或下方。这些埋入式植入物可以完全包围NFET（N型场效应晶体管）的PWELL（P型阱）。

2. 发明授权

US09728532B2 Clamp based ESD protection circuits 有权
公开(公告)号：US09728532B2
公开(公告)日：2017-08-08
申请号：US13446697
申请日：2012-04-13
申请人： Swaminathan Muthukrishnan , Nathaniel Peachey , Cody Hale , Ralph Williamson
发明人： Swaminathan Muthukrishnan , Nathaniel Peachey , Cody Hale , Ralph Williamson
IPC分类号： H02H9/00 , H01L27/02 , H02H9/04
CPC分类号： H01L27/0274 , H02H9/046
摘要： An electro-static discharge (ESD) protection circuit utilizes a gate-drain breakdown characteristic of high electron mobility transistors (HEMTs) in a dual stacked configuration to provide a discharge path for electro-static discharges, while having a minimal effect on the associated circuit which is being protected.

3. 发明授权

US08498166B1 Electro-static discharge power supply clamp with disablement latch 有权
标题翻译：具有禁用闩锁的静电放电电源钳
公开(公告)号：US08498166B1
公开(公告)日：2013-07-30
申请号：US12913060
申请日：2010-10-27
申请人： Nathaniel Peachey , Joseph Hubert Colles , Jeffrey D. Potts
发明人： Nathaniel Peachey , Joseph Hubert Colles , Jeffrey D. Potts
IPC分类号： G11C7/10 , G11C5/06 , G11C11/00
CPC分类号： G11C7/12 , G11C5/02 , G11C5/06 , G11C5/147 , G11C7/02 , G11C7/1051 , G11C7/1078 , G11C7/22 , G11C13/04 , H01L23/60 , H01L2924/0002 , H02H9/041 , H01L2924/00
摘要： The described devices, systems and methods include an electro-static discharge clamp with a latch to prevent false triggering of an electro-static discharge protection circuit in response to fluctuations in a power supply rail.
摘要翻译：所描述的装置，系统和方法包括具有闩锁的静电放电夹具，以防止电抗放电保护电路响应于电源轨的波动而错误触发。

4. 发明授权

US08373956B2 Low leakage electrostatic discharge protection circuit 失效
标题翻译：低泄漏静电放电保护电路
公开(公告)号：US08373956B2
公开(公告)日：2013-02-12
申请号：US12943980
申请日：2010-11-11
申请人： Michel J. Abou-Khalil , Kiran V. Chatty , Chee Kwang Quek , Robert J. Gauthier, Jr. , Nathaniel Peachey
发明人： Michel J. Abou-Khalil , Kiran V. Chatty , Chee Kwang Quek , Robert J. Gauthier, Jr. , Nathaniel Peachey
IPC分类号： H02H9/00 , H02H1/00 , H02H1/04 , H02H3/22 , H02H9/06
CPC分类号： H02H9/046
摘要： A circuit and method for electrostatic discharge (ESD) protection. The ESD protection circuit includes: a silicon control rectifier (SCR) connected between a first voltage rail and a second voltage rail; one or more diodes connected in series in a forward conduction direction between the first voltage rail and a source of a p-channel field effect transistor (PFET); a drain of the PFET connected to the SCR and connected to ground through a current trigger device; and a control circuit connected to the gate of the PFET.
摘要翻译：一种用于静电放电（ESD）保护的电路和方法。 ESD保护电路包括：连接在第一电压轨和第二电压轨之间的硅控制整流器（SCR）; 在第一电压轨和p沟道场效应晶体管（PFET）的源极之间沿正向传导方向串联连接的一个或多个二极管; 连接到SCR的PFET的漏极通过电流触发装置连接到地; 以及连接到PFET的栅极的控制电路。

5. 发明授权

US07881030B1 Enhancement-mode field effect transistor based electrostatic discharge protection circuit 有权
标题翻译：基于增强型场效应晶体管的静电放电保护电路
公开(公告)号：US07881030B1
公开(公告)日：2011-02-01
申请号：US12168179
申请日：2008-07-07
申请人： Jason Yuxin Li , Walter A. Wohlmuth , Swaminathan Muthukrishnan , Christian Rye Iversen , Nathaniel Peachey
发明人： Jason Yuxin Li , Walter A. Wohlmuth , Swaminathan Muthukrishnan , Christian Rye Iversen , Nathaniel Peachey
IPC分类号： H02H3/22
CPC分类号： H03F1/52 , H01Q1/50 , H03F2200/441
摘要： The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance, a drain-to-gate resistance, or both of the FET element, and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element and a resistive element. Therefore, the single FET element ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity of the ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.
摘要翻译：本发明涉及用于保护其它电路免受高电压ESD事件的静电放电（ESD）钳位电路。 ESD钳位电路可以包括作为钳位元件的场效应晶体管（FET）元件，其通过使用漏极到栅极电容，漏极到栅极电阻或者FET元件的两者以及电阻元件作为分压器来分压ESD电压以提供FET元件的触发栅极电压。在其最简单的实施例中，ESD钳位电路仅包括FET元件和电阻元件。因此，与其他ESD保护电路相比，单个FET元件ESD钳位电路可能较小。 ESD钳位电路的简单性可以使寄生电容最小化，从而在宽频率范围内最大化ESD钳位电路的线性度。

6. 发明申请

US20120262828A1 CLAMP BASED ESD PROTECTION CIRCUITS 有权
标题翻译：基于钳位的ESD保护电路
公开(公告)号：US20120262828A1
公开(公告)日：2012-10-18
申请号：US13446697
申请日：2012-04-13
申请人： Swaminathan Muthukrishnan , Nathaniel Peachey , Cody Hale , Ralph Williamson
发明人： Swaminathan Muthukrishnan , Nathaniel Peachey , Cody Hale , Ralph Williamson
IPC分类号： H02H9/04
CPC分类号： H01L27/0274 , H02H9/046
摘要： An electro-static discharge (ESD) protection circuit utilizes a gate-drain breakdown characteristic of high electron mobility transistors (HEMTs) in a dual stacked configuration to provide a discharge path for electro-static discharges, while having a minimal effect on the associated circuit which is being protected.
摘要翻译：静电放电（ESD）保护电路利用双重堆叠结构中的高电子迁移率晶体管（HEMT）的栅极 - 漏极击穿特性来提供用于静电放电的放电路径，同时对相关电路具有最小的影响正在受到保护。

7. 发明授权

US07929263B1 Unlatch feature for latching ESD protection circuit 有权
标题翻译：用于锁定ESD保护电路的解锁功能
公开(公告)号：US07929263B1
公开(公告)日：2011-04-19
申请号：US11832114
申请日：2007-08-01
申请人： Nathaniel Peachey , Carlos Gamero
发明人： Nathaniel Peachey , Carlos Gamero
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： The present invention is a latching electrostatic discharge (ESD) protection circuit that enables and latches an ESD clamping circuit upon an ESD event, and disables and un-latches the ESD clamping circuit upon either a drop in the DC supply voltage below a defined threshold or a time-out. The time-out protects against effects of inadvertent latching or any anomaly in which the latching ESD clamping circuit does not un-latch. An ESD event is a voltage spike between the DC supply voltage and ground wherein the ESD clamping circuit applies a low impedance between the DC supply voltage and ground to dissipate the energy contained in the voltage spike, thereby protecting adjacent circuitry.
摘要翻译：本发明是一种闭锁静电放电（ESD）保护电路，其在ESD事件时启用和锁存ESD钳位电路，并且在直流电源电压的下降低于定义的阈值时禁用和解锁ESD钳位电路，或超时超时保护可以防止无意锁定或任何异常，其中闩锁ESD钳位电路不会解锁。 ESD事件是DC电源电压和地之间的电压尖峰，其中ESD钳位电路在DC电源电压和地之间施加低阻抗以耗散包含在电压尖峰中的能量，从而保护相邻电路。

8. 发明授权

US07881029B1 Depletion-mode field effect transistor based electrostatic discharge protection circuit 有权
标题翻译：消耗型场效应晶体管的静电放电保护电路
公开(公告)号：US07881029B1
公开(公告)日：2011-02-01
申请号：US12168178
申请日：2008-07-07
申请人： Jason Yuxin Li , Walter A. Wohlmuth , Swaminathan Muthukrishnan , Christian Rye Iversen , Nathaniel Peachey
发明人： Jason Yuxin Li , Walter A. Wohlmuth , Swaminathan Muthukrishnan , Christian Rye Iversen , Nathaniel Peachey
IPC分类号： H02H3/22
CPC分类号： H03F1/52 , H01Q1/50 , H03F2200/441
摘要： The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance and a drain-to-gate resistance of the FET element and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element, a resistive element, a source-coupled level shifting diode, and a reverse protection diode. Therefore, the ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity of the ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.
摘要翻译：本发明涉及用于保护其它电路免受高电压ESD事件的静电放电（ESD）钳位电路。 ESD钳位电路可以包括作为钳位元件的场效应晶体管（FET）元件，其通过使用FET元件的漏极 - 栅极电容和漏极 - 栅极电阻和电阻元件作为电压来触发以分隔ESD电压以提供FET元件的触发栅极电压。在其最简单的实施例中，ESD钳位电路仅包括FET元件，电阻元件，源极耦合电平移位二极管和反向保护二极管。因此，与其他ESD保护电路相比，ESD钳位电路可能较小。 ESD钳位电路的简单性可以使寄生电容最小化，从而在宽频率范围内最大化ESD钳位电路的线性度。

9. 发明授权

US07593204B1 On-chip ESD protection circuit for radio frequency (RF) integrated circuits 失效
标题翻译：用于射频（RF）集成电路的片上ESD保护电路
公开(公告)号：US07593204B1
公开(公告)日：2009-09-22
申请号：US11609497
申请日：2006-12-12
申请人： Christian Rye Iversen , Swaminathan Muthukrishnan , Nathaniel Peachey
发明人： Christian Rye Iversen , Swaminathan Muthukrishnan , Nathaniel Peachey
IPC分类号： H02H9/00 , H02H1/00
CPC分类号： H02H9/046
摘要： Methods and apparatus for ESD protection of pseudomorphic high electron mobility transistor (pHEMT) circuitry are described. In one method, an ESD surge is detected at a trigger circuit. An ESD protection circuit is triggered. Current flow within the trigger circuit is limited and ESD energy is dispersed to a ground plane via the ESD protection circuit.
摘要翻译：描述了假型高电子迁移率晶体管（pHEMT）电路的ESD保护的方法和装置。在一种方法中，在触发电路处检测到ESD浪涌。触发ESD保护电路。触发电路内的电流受到限制，ESD能量通过ESD保护电路分散到接地层。

10. 发明申请

US20060250732A1 Transient pulse, substrate-triggered biCMOS rail clamp for ESD abatement 审中-公开
标题翻译：瞬态脉冲，衬底触发biCMOS导轨夹，用于ESD减轻
公开(公告)号：US20060250732A1
公开(公告)日：2006-11-09
申请号：US11123305
申请日：2005-05-06
申请人： Nathaniel Peachey
发明人： Nathaniel Peachey
IPC分类号： H02H9/00
CPC分类号： H01L27/0259
摘要： A circuit for protecting a circuit device against electrostatic discharge (ESD), power line, and voltage supply line surges. A transistor, diode, resistor, and capacitor are configured to clamp voltage pulses between the power and ground lines. The circuit is constructed using a single bipolar npn transistor formed using an isolated p-well.
摘要翻译：用于保护电路设备免受静电放电（ESD），电源线和电源线浪涌的电路。晶体管，二极管，电阻和电容器被配置为钳位电源和地线之间的电压脉冲。该电路使用一个使用一个隔离p阱形成的单极型npn晶体管构成。

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