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1. 发明申请

US20080233753A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR MANUFACTURING EQUIPMENT 有权
标题翻译：制造半导体器件和半导体制造设备的方法
公开(公告)号：US20080233753A1
公开(公告)日：2008-09-25
申请号：US12052288
申请日：2008-03-20
申请人： Naoki IDANI
发明人： Naoki IDANI
IPC分类号： B08B3/08 , B08B13/00 , H01L21/311
CPC分类号： H01L21/02065 , H01L21/02074 , H01L21/31053 , H01L21/3212 , Y10S438/906
摘要： A method of manufacturing a semiconductor device has polishing a film, and cleaning a polished surface by carrying out a first exposing the polished surface to an acidic first cleaning fluid having an effect of etching at least a partial region of the polished surface, and a second exposing the polished surface to an alkaline second cleaning fluid after the first exposing.
摘要翻译：制造半导体器件的方法具有抛光膜，并且通过首先将抛光表面暴露于具有蚀刻抛光表面的至少一部分区域的作用的酸性第一清洗流体来清洁抛光表面，以及第二在第一次曝光之后将抛光表面暴露于碱性第二清洗液。

2. 发明申请

US20080064308A1 Polishing apparatus and manufacturing method of an electronic apparatus 审中-公开
标题翻译：电子设备的抛光设备和制造方法
公开(公告)号：US20080064308A1
公开(公告)日：2008-03-13
申请号：US11653953
申请日：2007-01-17
申请人： Naoki Idani
发明人： Naoki Idani
IPC分类号： B24B29/00
CPC分类号： B24B37/32
摘要： A polishing apparatus that polishes a substrate to be processed includes a rotary polishing table carrying a polishing pad on a surface thereof, and a polishing head that urges the substrate to be processed against the polishing pad while rotating the substrate to be processed, wherein the polishing head holds the substrate to be processed by a retainer ring, the retainer ring includes: a resin ring formed of a resin and contacted with the polishing pad; and an upper part ring that holds the resin ring, at least first and second patterns of convex shape or concave shape are formed on a junction surface of the upper part ring where the upper part ring is contacted with the resin ring, at least third and fourth patterns of concave shape or convex shape are formed on a junction surface of the resin ring where the resin ring makes contact with the upper electrode, in a manner complementary to the patterns of the convex shape or concave shape formed on the junction surface of the upper electrode.
摘要翻译：对被处理基板进行抛光的抛光装置包括：在其表面承载有抛光垫的旋转研磨台，以及抛光头，其在旋转待处理基板的同时将衬底加工成抛光垫，其中抛光头部保持用保持环加工的基板，保持环包括：由树脂形成并与抛光垫接触的树脂环; 以及保持树脂环的上部环，至少在上部环与树脂环接触的上部环的接合面上形成至少第一和第二凸起形状或凹形的图案，至少第三和第三图案在树脂环与上电极接触的树脂环的接合面上形成凹形或凸形的第四图案，以与形成在第二表面上的凸形或凹形的图案互补的方式形成上电极。

3. 发明申请

US20070007246A1 Manufacture of semiconductor device with CMP 审中-公开
标题翻译：制造具有CMP的半导体器件
公开(公告)号：US20070007246A1
公开(公告)日：2007-01-11
申请号：US11264240
申请日：2005-11-02
申请人： Naoki Idani
发明人： Naoki Idani
IPC分类号： C03C15/00 , B44C1/22 , H01L21/461
CPC分类号： H01L21/31053 , B24B37/042 , H01L21/02065 , H01L21/823871
摘要： A manufacture method for a semiconductor device, includes the steps of: in CMP for forming STI, (a) polishing the surface of a film formed on a semiconductor substrate until the surface of the film is planarized, by using first abrasive containing cerium dioxide abrasive grains and additive of interfacial active agent; (b) after the step (a), polishing the surface of the film is polished by using second abrasive having a physical polishing function; and (c) after the step (b), polishing the surface of the film by using third abrasive containing cerium dioxide abrasive grains, additive of interfacial active agent, and diluent. The manufacture method further includes the steps of: (p) forming wirings above the semiconductor substrate; (q) depositing a first insulating film by HDP CVD, the first insulating film burying the wirings; (r) depositing a second insulating film above the first insulating film by a deposition method different from HDP-CVD; and (s) planarizing the second insulating film by chemical mechanical polishing using abrasive containing cerium dioxide abrasive grains. It is possible to solve an issue of a left film after polishing newly found from a large size substrate and to suppress a distribution of thicknesses of an interlayer insulating film at a wafer level.
摘要翻译：一种半导体器件的制造方法，包括以下步骤：在CMP中形成STI，（a）研磨形成在半导体衬底上的膜的表面，直到膜的表面平坦化为止，使用含有二氧化铈研磨剂界面活性剂的颗粒和添加剂; （b）在步骤（a）之后，通过使用具有物理抛光功能的第二磨料抛光抛光所述膜的表面; 和（c）在步骤（b）之后，通过使用含有二氧化铈磨料颗粒，界面活性剂添加剂和稀释剂的第三磨料来研磨膜的表面。制造方法还包括以下步骤：（p）在半导体衬底上形成布线; （q）通过HDP CVD沉积第一绝缘膜，所述第一绝缘膜掩埋所述布线; （r）通过不同于HDP-CVD的沉积方法在第一绝缘膜上方沉积第二绝缘膜; 和通过使用包含二氧化铈磨料颗粒的磨料进行化学机械抛光来平面化第二绝缘膜。可以解决从大尺寸基板新发现的抛光后的左膜的问题，并抑制晶片级的层间绝缘膜的厚度分布。

4. 发明申请

US20060113628A1 Designing and fabrication of a semiconductor device 有权
标题翻译：设计和制造半导体器件
公开(公告)号：US20060113628A1
公开(公告)日：2006-06-01
申请号：US11333212
申请日：2006-01-18
申请人： Naoki Idani , Toshiyuki Karasawa , Ryota Nanjo
发明人： Naoki Idani , Toshiyuki Karasawa , Ryota Nanjo
IPC分类号： H01L29/00
CPC分类号： G06F17/5068 , H01L21/31053
摘要： Designing method of an electronic device subjected to a chemical mechanical polishing process in a fabrication process thereof is conducted according to the steps of: dividing a substrate surface into first sub-regions; optimizing a coverage ratio of hard-to-polish regions in the first sub-regions to fall in a first predetermined range corresponding to the first sub-regions; dividing the substrate surface into second sub-regions different from the first sub-regions; and optimizing a coverage ratio of the hard-to-polish regions in the second sub-regions to fall in a second predetermined range corresponding to the second sub-regions, wherein patterns having a shorter edge of 5 μm or less are excluded from the optimization.
摘要翻译：根据以下步骤进行在其制造工艺中进行化学机械抛光工艺的电子器件的设计方法：将衬底表面分成第一子区; 优化所述第一子区域中的硬抛光区域的覆盖率落在对应于所述第一子区域的第一预定范围内; 将基板表面分成与第一子区域不同的第二子区域; 并且优化所述第二子区域中的所述硬抛光区域的覆盖率落入对应于所述第二子区域的第二预定范围中，其中具有5μm或更小边缘的边缘的图案被从所述优化中排除。

5. 发明授权

US08496758B2 Cleaning apparatus and cleaning method for wafer 有权
标题翻译：晶圆清洗装置及清洗方法
公开(公告)号：US08496758B2
公开(公告)日：2013-07-30
申请号：US13032817
申请日：2011-02-23
申请人： Naoki Idani
发明人： Naoki Idani
IPC分类号： B08B7/00
CPC分类号： H01L21/67046 , B08B1/00 , B08B3/04
摘要： A front surface of the wafer is contacted with a straight-shaped front surface cleaning brush, and a pressure is applied on the front surface cleaning brush from both ends to enlarge the diameters in both end portions of the front surface cleaning brush. The front surface cleaning brush rotates with a shaft being an axis. An inner surface of the front surface cleaning brush is directly in contact with a surface of the shaft. The front surface cleaning brush is composed of a single structure made of synthetic resin.
摘要翻译：晶片的前表面与直线形的前表面清洁刷接触，并且从两端向前表面清洁刷施加压力，以增大前表面清洁刷的两端部的直径。前表面清洁刷以轴为轴旋转。前表面清洁刷的内表面与轴的表面直接接触。前表面清洁刷由合成树脂制成的单一结构构成。

6. 发明申请

US20120001344A1 SEMICONDUCTOR DEVICE MANUFACTURE METHOD AND SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US20120001344A1
公开(公告)日：2012-01-05
申请号：US13025776
申请日：2011-02-11
申请人： Satoshi TAKESAKO , Naoki IDANI
发明人： Satoshi TAKESAKO , Naoki IDANI
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/7684 , H01L21/31144 , H01L21/3212 , H01L21/76808 , H01L21/76813 , H01L23/522 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacture method includes: forming an insulating film above a semiconductor substrate; etching the insulating film to form a dummy groove having a first depth, a wiring groove having a second depth deeper than the first depth, and a via hole to be disposed on a bottom of the wiring groove; depositing a conductive material in the dummy groove, wiring groove and via hole and above the insulating film; and polishing and removing the conductive material above the insulating film.
摘要翻译：半导体器件制造方法包括：在半导体衬底上形成绝缘膜; 蚀刻绝缘膜以形成具有第一深度的虚设槽，具有比第一深度更深的第二深度的布线槽和布置在布线槽的底部的通孔; 在虚设槽，布线槽和通孔中以及绝缘膜上方沉积导电材料; 并且在绝缘膜上抛光和去除导电材料。

7. 发明授权

US07951715B2 Semiconductor device fabrication method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US07951715B2
公开(公告)日：2011-05-31
申请号：US10823729
申请日：2004-04-14
申请人： Takashi Watanabe , Naoki Idani , Toshiyuki Isome
发明人： Takashi Watanabe , Naoki Idani , Toshiyuki Isome
IPC分类号： H01L21/302
CPC分类号： B24B37/013 , B24B37/042 , B24B49/16 , H01L21/31053 , H01L21/3212 , H01L21/76229 , H01L21/76819 , H01L21/7684
摘要： The method comprises the step polishing the surface of a film-to-be-polished formed over a semiconductor substrate 10 with a polishing pad while a polishing slurry containing abrasive grains, and an additive of a surfactant is being supplied onto the polishing pad 104 to thereby planarize the surface of the film-to-be-polished, and the step of further polishing the surface of the film-to-be-polished with the polishing pad while the polishing slurry and water are being supplied onto the polishing pad, after the surface of the film-to-be-polished has been planarized. In the finishing polish, not only deionized water but also the polishing slurry are supplied on to the polishing pad, a position for the polishing slurry to be supplied to and a position for the deionized water to be supplied to are suitably set, and a ratio of a supply amount of the polishing slurry and a supply amount of the deionized water is suitably set, whereby the intra-plane film thickness of the film-to-be-polished as finish-polished can be uniform.
摘要翻译：该方法包括用抛光垫在半导体衬底10上形成的待抛光膜的表面进行抛光，同时将含有磨粒的抛光浆料和表面活性剂添加剂供应到抛光垫104至从而使被研磨的膜的表面平坦化，在抛光浆料和水被供给到研磨垫上之后，用研磨垫进一步研磨被研磨膜的表面的工序，之后，被抛光膜的表面已被平坦化。在精整抛光中，不仅将去离子水，而且将抛光浆料供给到抛光垫，适当地设置要供给的抛光浆料的位置和供给的去离子水的位置，抛光浆的供给量和去离子水的供给量适当设定，由此精抛光的被研磨膜的面内膜厚可以均匀。

8. 发明申请

US20070215975A1 Method of fabricating semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20070215975A1
公开(公告)日：2007-09-20
申请号：US11511406
申请日：2006-08-29
申请人： Naoki Idani , Satoshi Inagaki
发明人： Naoki Idani , Satoshi Inagaki
IPC分类号： H01L23/58 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/76205
摘要： Aiming at obtaining stable and uniform element isolation characteristics without forming the oxide film liner or the like on the inner wall surface of the isolation trench, and ensuring a sufficient level of adhesiveness of the insulating material filled in the isolation trench, and obtaining uniform and excellent element isolation characteristics and a sufficient level of adhesiveness of the buried insulating material, even when applied to large-diameter semiconductor substrates, a thermal oxide film is formed on the inner wall surface of isolation trenches, and a silicon semiconductor substrate is then annealed using a lamp annealer at a temperature higher than in the process of forming thermal oxide film, typically at 950° C. for a predetermined short time (30 seconds herein, for example), wherein the annealing modifies at least the surficial portion of thermal oxide film to have a further complete and uniform state of oxidation.
摘要翻译：为了获得稳定且均匀的元件隔离特性，而不在隔离沟槽的内壁表面上形成氧化膜衬垫等，并且确保填充在隔离沟槽中的绝缘材料具有足够的粘附性，并且获得均匀且优异的元件隔离特性和埋藏绝缘材料的充分的粘附性，即使在大直径半导体基板上使用时，在隔离沟槽的内壁面形成热氧化膜，然后使用通常在950℃下预定的短时间（例如在此为30秒），其中退火将至少热氧化膜的表面部分修饰为具有进一步完整和均匀的氧化状态。

9. 发明授权

US07250644B2 Electronic device and method for designing the same 有权
标题翻译：电子设备及其设计方法
公开(公告)号：US07250644B2
公开(公告)日：2007-07-31
申请号：US11081727
申请日：2005-03-17
申请人： Naoki Idani
发明人： Naoki Idani
IPC分类号： H01L27/10 , H01L29/739 , H01L29/73 , H01L29/76 , H01L29/94
CPC分类号： H01L27/0207
摘要： The electronic device includes a plurality of layout regions each including a plurality of patterns defined by a buried structure buried in a substrate. For each of the layout regions, in each of the layout regions, the minimum space between the patterns, and a maximum area percentage allowed for the patterns in the layout region are defined based on a size of the layout region. In larger one of the layout regions, the minimum space between the patterns in the region is set larger.
摘要翻译：电子设备包括多个布局区域，每个布局区域包括由掩埋在衬底中的掩埋结构限定的多个图案。对于每个布局区域，在每个布局区域中，基于布局区域的大小来定义布局区域中的图案之间的最小空间和允许布局区域中的图案的最大面积百分比。在较大的一个布局区域中，该区域中的图案之间的最小空间被设置得较大。

10. 发明授权

US06854095B2 Designing method and a manufacturing method of an electronic device 有权
标题翻译：电子设备的设计方法和制造方法
公开(公告)号：US06854095B2
公开(公告)日：2005-02-08
申请号：US10446692
申请日：2003-05-29
申请人： Naoki Idani
发明人： Naoki Idani
IPC分类号： G11B5/31 , G06F9/45 , G06F17/50 , H01L21/3105 , H01L21/76 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G06F17/5068 , G06F2217/12 , G11B5/3163 , H01L21/31053 , Y02P90/265
摘要： A designing method of an electronic device is provided. An STI structure, a wiring structure and the like defines a first area ratio range and a second area ratio range that are permissible in order to obtain satisfactory polishing results. A region to be polished is divided into first smaller areas, an area ratio of each of which is adjusted to meet the first area ratio range. The region to be polished is divided into second smaller areas, which are larger than the first smaller areas. An area ratio of each is adjusted to meet the second area ratio range, thereby providing satisfactory planarity of the region to be polished without producing depressions due to erosion caused by differing polishing speeds caused by differing densities of the regions to be polished.
摘要翻译：提供了一种电子设备的设计方法。 STI结构，布线结构等限定为了获得令人满意的抛光结果而允许的第一面积比范围和第二面积比范围。要被抛光的区域被分成第一较小区域，每个区域的面积比被调节以满足第一面积比范围。要抛光的区域被分为比第一较小区域大的第二较小区域。调整面积比以满足第二面积比范围，从而提供待抛光区域的令人满意的平面度，而不会由于待研磨区域的不同密度引起的不同抛光速度而产生由于侵蚀引起的凹陷。

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