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1. 发明授权

US08264043B1 Protection of integrated circuit gates during metallization processes 有权
标题翻译：在金属化过程中保护集成电路门
公开(公告)号：US08264043B1
公开(公告)日：2012-09-11
申请号：US11411064
申请日：2006-04-25
申请人： Sanjay Rekhi , Nagendra Cherukupalli , Paul D. Keswick
发明人： Sanjay Rekhi , Nagendra Cherukupalli , Paul D. Keswick
IPC分类号： H01L23/60
CPC分类号： H01L27/0255 , H01L27/0266 , Y10S438/901
摘要： In one embodiment, a first transistor is configured to switch ON to discharge accumulated charges on an interconnect line during a metallization process. This advantageously protects a second transistor, which is coupled to the interconnect line, from charge buildup. The gate of the first transistor may be coupled to the interconnect line by way of a coupling capacitor. The gate of the first transistor may remain floating during the metallization process, and subsequently coupled to ground at a topmost metal level. The metallization process may be physical vapor deposition, for example.
摘要翻译：在一个实施例中，第一晶体管被配置为在金属化处理期间接通以在互连线上排放累积电荷。这有利地保护耦合到互连线的第二晶体管免受电荷积聚。第一晶体管的栅极可以通过耦合电容耦合到互连线。第一晶体管的栅极可以在金属化过程期间保持浮置，并且随后在最高金属水平处耦合到地。金属化工艺可以是例如物理气相沉积。

2. 发明授权

US10125961B2 Platform to integrate sensors into light bulbs 有权
公开(公告)号：US10125961B2
公开(公告)日：2018-11-13
申请号：US14952150
申请日：2015-11-25
申请人： Jason Slosberg , Nagendra Cherukupalli , Michael R. Loeb
发明人： Jason Slosberg , Nagendra Cherukupalli , Michael R. Loeb
IPC分类号： F21V23/04 , F21V3/02 , F21V17/02 , H05B33/00 , F21K9/232 , F21V33/00 , F21Y115/10
摘要： According to some embodiments, a light bulb may include a base adapted to be coupled to a power socket, lighting circuitry supporting at least one lighting element to provide illumination, a communication element to exchange information with at least one remote device, and a receiving portion. An extendable sensor mount may include a first end attached to be attached to the receiving portion of the light bulb and a second end, opposite the first end, extendable with respect to the light bulb. A sensor may be coupled to the second end of the extendable sensor mount, and data collected by the sensor may be transmitted to the at least one remote device via the communication element of the light bulb.

3. 发明申请

US20170146197A1 PLATFORM TO INTEGRATE SENSORS INTO LIGHT BULBS 审中-公开
公开(公告)号：US20170146197A1
公开(公告)日：2017-05-25
申请号：US14952150
申请日：2015-11-25
申请人： Jason Slosberg , Nagendra Cherukupalli , Michael R. Loeb
发明人： Jason Slosberg , Nagendra Cherukupalli , Michael R. Loeb
IPC分类号： F21K99/00 , F21V29/70 , F21S8/02 , F21V23/04 , F21V19/00 , F21V3/02
CPC分类号： F21V23/045 , F21K9/232 , F21V3/02 , F21V17/02 , F21V33/0076 , F21Y2115/10 , H05B33/00
摘要： According to some embodiments, a light bulb may include a base adapted to be coupled to a power socket, lighting circuitry supporting at least one lighting element to provide illumination, a communication element to exchange information with at least one remote device, and a receiving portion. An extendable sensor mount may include a first end attached to be attached to the receiving portion of the light bulb and a second end, opposite the first end, extendable with respect to the light bulb. A sensor may be coupled to the second end of the extendable sensor mount, and data collected by the sensor may be transmitted to the at least one remote device via the communication element of the light bulb.

4. 发明授权

US07392495B1 Method and system for providing hybrid clock distribution 有权
标题翻译：提供混合时钟分配的方法和系统
公开(公告)号：US07392495B1
公开(公告)日：2008-06-24
申请号：US10218504
申请日：2002-08-13
申请人： Nagendra Cherukupalli , Rakesh Mehrotra
发明人： Nagendra Cherukupalli , Rakesh Mehrotra
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62
摘要： A method and system for providing hybrid clock distribution is disclosed. The distribution architecture uses a grid distribution at the top level and a balanced buffer tree distribution at the block level. The method includes determining the block layout of an integrated circuit which employs a clock distribution network for distributing clock signals. In addition the method includes providing a mesh distribution network for delivering clock signals to integrated circuit blocks of the integrated circuit. Thereafter, a balanced tree distribution network for delivering clock signals to the components of each block of the integrated circuit is provided. The top level grid provides predictable min/max skew at the top level and the remainder skew budget can be applied to the blocks.
摘要翻译：公开了一种用于提供混合时钟分配的方法和系统。分布架构使用顶层的网格分布和块级别的平衡缓冲树分布。该方法包括确定采用时钟分配网络来分配时钟信号的集成电路的块布局。此外，该方法包括提供用于将时钟信号传送到集成电路的集成电路块的网格分配网络。此后，提供了用于将时钟信号传送到集成电路的每个块的组件的平衡树分配网络。顶级网格在顶层提供可预测的最小/最大偏移，并且余数偏差预算可以应用于块。

5. 发明授权

US07033900B1 Protection of integrated circuit gates during metallization processes 有权
标题翻译：在金属化过程中保护集成电路门
公开(公告)号：US07033900B1
公开(公告)日：2006-04-25
申请号：US10807909
申请日：2004-03-24
申请人： Sanjay Rekhi , Nagendra Cherukupalli , Paul D. Keswick
发明人： Sanjay Rekhi , Nagendra Cherukupalli , Paul D. Keswick
IPC分类号： H01L21/8222
CPC分类号： H01L27/0255 , H01L27/0266 , Y10S438/901
摘要： In one embodiment, a first transistor is configured to switch ON to discharge accumulated charges on an interconnect line during a metallization process. This advantageously protects a second transistor, which is coupled to the interconnect line, from charge buildup. The gate of the first transistor may be coupled to the interconnect line by way of a coupling capacitor. The gate of the first transistor may remain floating during the metallization process, and subsequently coupled to ground at a topmost metal level. The metallization process may be physical vapor deposition, for example.
摘要翻译：在一个实施例中，第一晶体管被配置为在金属化处理期间接通以在互连线上排出累积电荷。这有利地保护耦合到互连线的第二晶体管免受电荷积聚。第一晶体管的栅极可以通过耦合电容耦合到互连线。第一晶体管的栅极可以在金属化过程期间保持浮置，并且随后在最高金属水平处耦合到地。金属化工艺可以是例如物理气相沉积。

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