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1. 外观设计

USD780682S1 Tire 有权
公开(公告)号：USD780682S1
公开(公告)日：2017-03-07
申请号：US29525913
申请日：2015-05-04
申请人： Mingming Zhao , Wen Sun , Yixin Zhang , Junjie Liu , Junrui Wan , Xiaoyun Li , Na Bai
设计人： Mingming Zhao , Wen Sun , Yixin Zhang , Junjie Liu , Junrui Wan , Xiaoyun Li , Na Bai

2. 发明授权

US08559213B2 Sub-threshold memory cell circuit with high density and high robustness 有权
标题翻译：子阈值存储单元电路具有高密度和高鲁棒性
公开(公告)号：US08559213B2
公开(公告)日：2013-10-15
申请号：US13322859
申请日：2009-08-13
申请人： Jun Yang , Na Bai , Jie Li , Chen Hu , Longxing Shi
发明人： Jun Yang , Na Bai , Jie Li , Chen Hu , Longxing Shi
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A high-density and high-robustness sub-threshold memory cell circuit, having two PMOS transistors P1 and P2 and five NMOS transistors N1˜N5, wherein, the each base electrode of the two PMOS transistors and NMOS transistors N3, N4, and N5 is connected with the local grid electrode respectively; the base electrode of the NMOS transistors N1 and N2, are grounded respectively; the NMOS transistor N1 form an phase inverter with the PMOS transistor P1, and the NMOS transistor N2 form another phase inverter with the PMOS transistor P2; the two phase inverters are connected with each other in a cross coupling manner via the cut-off NMOS transistor N5, the output end of the phase inverter N1 and P1 directly connected to the input end of the phase inverter N2 and P2, and the output end of the phase inverter N2 and P2 connected to the input end of the phase inverter N1 and P1 via the cut-off NMOS transistor N5; the NMOS transistor N3 is connected with the write bit line (WBL) of the phase inverter N1 and P1, and the NMOS transistor N4 is connected with the NOT WBL and read word line (RWL) of the phase inverter N2 and P2.
摘要翻译：具有两个PMOS晶体管P1和P2以及五个NMOS晶体管N1〜N5的高密度和高鲁棒性子阈值存储单元电路，其中，两个PMOS晶体管和NMOS晶体管N3，N4和N5的每个基极分别与局部栅电极连接; NMOS晶体管N1和N2的基极分别接地; NMOS晶体管N1与PMOS晶体管P1形成相位逆变器，NMOS晶体管N2与PMOS晶体管P2形成另一个反相器; 两相逆变器通过截止NMOS晶体管N5，直流连接到相位逆变器N2和P2的输入端的相位反相器N1和P1的输出端以交叉耦合方式彼此连接，并且输出通过截止NMOS晶体管N5连接到相位反相器N1和P1的输入端的相位逆变器N2和P2的端部; NMOS晶体管N3与相位反相器N1和P1的写入位线（WBL）连接，NMOS晶体管N4与相位逆变器N2和P2的NOT WBL和读出字线（RWL）连接。

3. 发明授权

US08803580B2 Power-on-reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage 有权
标题翻译：上电复位（POR）电路具有零稳态电流消耗和稳定的上拉电压
公开(公告)号：US08803580B2
公开(公告)日：2014-08-12
申请号：US13704184
申请日：2011-10-17
申请人： Longxing Shi , Weiwei Shan , Peng Cao , Na Bai , Xuexiang Wang , Tao Zhao
发明人： Longxing Shi , Weiwei Shan , Peng Cao , Na Bai , Xuexiang Wang , Tao Zhao
IPC分类号： H03L7/00 , H03K3/02
CPC分类号： H03K17/20 , H03K17/223
摘要： The present invention discloses a Power-On-Reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage. The POR circuit achieves zero steady-state current consumption during steady operation after the POR process by cutting off a power supply to a band-gap comparator circuit and a current comparator circuit after the POR process. The present invention has high reliability and stable pull-up voltage, is less susceptible to the impact of power-on rate of power supply, temperature, and process variation, has very low steady-state power consumption, and can be integrated in a SOC chip in low-power consumption applications.
摘要翻译：本发明公开了一种具有零稳态电流消耗和稳定上拉电压的上电复位（POR）电路。在POR处理之后，通过在POR处理之后切断对带隙比较器电路和电流比较器电路的电源，POR电路在稳定运行期间实现零稳态电流消耗。本发明具有高可靠性和稳定的上拉电压，较不容易受到电源上电速率，温度和工艺变化的影响，具有非常低的稳态功耗，并且可以集成在SOC 芯片在低功耗应用中。

4. 发明申请

US20140097873A1 POWER-ON-RESET (POR) CIRCUIT WITH ZERO STEADY-STATE CURRENT CONSUMPTION AND STABLE PULL-UP VOLTAGE 有权
标题翻译：具有零稳态电流消耗和稳定上拉电压的上电复位（POR）电路
公开(公告)号：US20140097873A1
公开(公告)日：2014-04-10
申请号：US13704184
申请日：2011-10-17
申请人： Longxing Shi , Welwei Shan , Peng Cao , Na Bai , Xuexiang Wang , Tao Zhao
发明人： Longxing Shi , Welwei Shan , Peng Cao , Na Bai , Xuexiang Wang , Tao Zhao
IPC分类号： H03K17/20
CPC分类号： H03K17/20 , H03K17/223
摘要： The present invention discloses a Power-On-Reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage. The POR circuit achieves zero steady-state current consumption during steady operation after the POR process by cutting off a power supply to a band-gap comparator circuit and a current comparator circuit after the POR process. The present invention has high reliability and stable pull-up voltage, is less susceptible to the impact of power-on rate of power supply, temperature, and process variation, has very low steady-state power consumption, and can be integrated in a SOC chip in low-power consumption applications.
摘要翻译：本发明公开了一种具有零稳态电流消耗和稳定上拉电压的上电复位（POR）电路。在POR处理之后，通过在POR处理之后切断对带隙比较器电路和电流比较器电路的电源，POR电路在稳定运行期间实现零稳态电流消耗。本发明具有高可靠性和稳定的上拉电压，较不容易受到电源上电速率，温度和工艺变化的影响，具有非常低的稳态功耗，并且可以集成在SOC 芯片在低功耗应用中。

5. 发明申请

US20120069650A1 SUB-THRESHOLD MEMORY CELL CIRCUIT WITH HIGH DENSITY AND HIGH ROBUSTNESS 有权
标题翻译：具有高密度和高可靠性的子阈值存储单元电路
公开(公告)号：US20120069650A1
公开(公告)日：2012-03-22
申请号：US13322859
申请日：2009-08-13
申请人： Jun Yang , Na Bai , Jie Li , Chen Hu , Longxing Shi
发明人： Jun Yang , Na Bai , Jie Li , Chen Hu , Longxing Shi
IPC分类号： G11C11/34
CPC分类号： G11C11/412
摘要： A high-density and high-robustness sub-threshold memory cell circuit, having two PMOS transistors P1 and P2 and five NMOS transistors N1˜N5, wherein, the each base electrode of the two PMOS transistors and NMOS transistors N3, N4, and N5 is connected with the local grid electrode respectively; the base electrode of the NMOS transistors N1 and N2, are grounded respectively; the NMOS transistor N1 form an phase inverter with the PMOS transistor P1, and the NMOS transistor N2 form another phase inverter with the PMOS transistor P2; the two phase inverters are connected with each other in a cross coupling manner via the cut-off NMOS transistor N5, the output end of the phase inverter N1 and P1 directly connected to the input end of the phase inverter N2 and P2, and the output end of the phase inverter N2 and P2 connected to the input end of the phase inverter N1 and P1 via the cut-off NMOS transistor N5; the NMOS transistor N3 is connected with the write bit line (WBL) of the phase inverter N1 and P1, and the NMOS transistor N4 is connected with the NOT WBL and read word line (RWL) of the phase inverter N2 and P2.
摘要翻译：具有两个PMOS晶体管P1和P2以及五个NMOS晶体管N1〜N5的高密度和高鲁棒性子阈值存储单元电路，其中，两个PMOS晶体管和NMOS晶体管N3，N4和N5的每个基极分别与局部栅电极连接; NMOS晶体管N1和N2的基极分别接地; NMOS晶体管N1与PMOS晶体管P1形成相位逆变器，NMOS晶体管N2与PMOS晶体管P2形成另一个反相器; 两相逆变器通过截止NMOS晶体管N5，直流连接到相位逆变器N2和P2的输入端的相位反相器N1和P1的输出端以交叉耦合方式彼此连接，并且输出通过截止NMOS晶体管N5连接到相位反相器N1和P1的输入端的相位逆变器N2和P2的端部; NMOS晶体管N3与相位反相器N1和P1的写入位线（WBL）连接，NMOS晶体管N4与相位逆变器N2和P2的NOT WBL和读出字线（RWL）连接。

6. 发明申请

US20120069635A1 CAPACITY AND DENSITY ENHANCEMENT CIRCUIT FOR SUB-THRESHOLD MEMORY UNIT ARRAY 有权
标题翻译：容量和密度增强型电路存储单元阵列
公开(公告)号：US20120069635A1
公开(公告)日：2012-03-22
申请号：US13322114
申请日：2009-08-18
申请人： Jie Li , Na Bai , Ming Ling , Aiguo Bu , Chao Wang , Chen Hu
发明人： Jie Li , Na Bai , Ming Ling , Aiguo Bu , Chao Wang , Chen Hu
IPC分类号： G11C11/24
CPC分类号： G11C11/412 , G11C7/12
摘要： A capacity and density enhancement circuit for a sub-threshold memory unit array which can decrease the drain current in the bit lines and enhance the pull-up capability of memory cells. The capacity and density enhancement circuit is composed of a first enhancement transistor, a second enhancement transistor, a first mask transmission gate, a second mask transmission gate, a first logic memory capacitor and a second logic memory capacitor.
摘要翻译：一种用于子阈值存储单元阵列的容量和密度增强电路，其可以减小位线中的漏极电流并增强存储器单元的上拉能力。容量和密度增强电路由第一增强晶体管，第二增强晶体管，第一掩模传输栅极，第二掩模传输栅极，第一逻辑存储电容器和第二逻辑存储电容器组成。

7. 发明授权

US08345468B2 Capacity and density enhancement circuit for sub-threshold memory unit array 有权
标题翻译：用于子阈值存储单元阵列的容量和密度增强电路
公开(公告)号：US08345468B2
公开(公告)日：2013-01-01
申请号：US13322114
申请日：2009-08-18
申请人： Jie Li , Na Bai , Ming Ling , Aiguo Bu , Chao Wang , Chen Hu
发明人： Jie Li , Na Bai , Ming Ling , Aiguo Bu , Chao Wang , Chen Hu
IPC分类号： G11C11/24
CPC分类号： G11C11/412 , G11C7/12
摘要： A capacity and density enhancement circuit for a sub-threshold memory unit array which can decrease the drain current in the bit lines and enhance the pull-up capability of memory cells. The capacity and density enhancement circuit is composed of a first enhancement transistor, a second enhancement transistor, a first mask transmission gate, a second mask transmission gate, a first logic memory capacitor and a second logic memory capacitor.
摘要翻译：一种用于子阈值存储单元阵列的容量和密度增强电路，其可以减小位线中的漏极电流并增强存储器单元的上拉能力。容量和密度增强电路由第一增强晶体管，第二增强晶体管，第一掩模传输栅极，第二掩模传输栅极，第一逻辑存储电容器和第二逻辑存储电容器组成。

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