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    • 5. 发明授权
    • Chip layout for implementing arbitrated high speed switching access of pluralities of I/O data ports to internally cached DRAM banks and the like
    • 用于实现多个I / O数据端口到内部高速缓存的DRAM存储体等的仲裁高速切换访问的芯片布局
    • US06237130B1
    • 2001-05-22
    • US09182268
    • 1998-10-29
    • Satish SomanZbigniew OpalkaMukesh Chatter
    • Satish SomanZbigniew OpalkaMukesh Chatter
    • G06F1750
    • G11C5/025G06F12/0893
    • A novel chip layout for a network wherein pluralities of I/O data ports are each connected to transmit/receive SRAM buffer banks operable under arbitration units to access pluralities of internally cached DRAM banks via internal busses to enable switching data connections amongst all data ports through the appropriate buffers, the chip layout having, data ports substantially symmetrically placed with each data port connected to each arbitration unit and each transmit/receive buffer bank, and with each data port enabled to write into any DRAM bank, with the connections being effected such that each data port is substantially symmetric with respect to DRAM bank, arbitration unit and transmit/receive buffer banks and busses; and with timing clocks centrally placed on the chip to minimize clock skew by symmetric clock distribution.
    • 一种用于网络的新型芯片布局,其中多个I / O数据端口各自连接到可在仲裁单元下操作的发送/接收SRAM缓冲器组,以经由内部总线访问多个内部缓存的DRAM组,以实现在所有数据端口之间切换数据连接, 适当的缓冲器,芯片布局具有与连接到每个仲裁单元和每个发送/接收缓冲器组的每个数据端口基本上对称地布置的数据端口,并且使得每个数据端口能够写入任何DRAM组,其中连接正在进行 每个数据端口相对于DRAM组,仲裁单元和发送/接收缓冲器组和总线基本对称; 并且定时时钟集中放置在芯片上,以通过对称时钟分配来最小化时钟偏移。