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    • 6. 发明授权
    • Low etch pit density (EPD) semi-insulating III-V wafers
    • 低蚀刻坑密度(EPD)半绝缘III-V晶片
    • US08361225B2
    • 2013-01-29
    • US13207291
    • 2011-08-10
    • Weiguo LiuMorris S. YoungM. Hani Badawi
    • Weiguo LiuMorris S. YoungM. Hani Badawi
    • C01B30/02
    • C30B11/00C30B29/42H01L21/3228Y10T428/24372
    • Systems and methods of manufacturing wafers are disclosed using a low EPD crystal growth process and a wafer annealing process are provided resulting in III-V/GaAs wafers that provide higher device yields from the wafer. In one exemplary implementation, there is provided a method of manufacturing a group III based material with a low etch pit density (EPD). Moreover, the method includes forming polycrystalline group III based compounds, and performing vertical gradient freeze crystal growth using the polycrystalline group III based compounds. Other exemplary implementations may include controlling temperature gradient(s) during formation of the group III based crystal to provide very low etch pit density.
    • 公开了使用低EPD晶体生长工艺制造晶圆的系统和方法,并且提供晶片退火工艺,从而产生从晶片提供更高的器件产量的III-V / GaAs晶片。 在一个示例性实施方案中,提供了制造具有低蚀刻坑密度(EPD)的基于III族的材料的方法。 此外,该方法包括形成多晶III族化合物,并使用多晶III族化合物进行垂直梯度冷冻晶体生长。 其它示例性实施方案可以包括在形成基于III族的晶体期间控制温度梯度以提供非常低的蚀刻坑密度。