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1. 发明授权

US07868892B2 Data processor and graphic data processing device 有权
标题翻译：数据处理器和图形数据处理设备
公开(公告)号：US07868892B2
公开(公告)日：2011-01-11
申请号：US12237112
申请日：2008-09-24
申请人： Hirotaka Hara , Hiroyuki Hamasaki , Mitsuhiro Saeki , Kazuhiro Hirade , Makoto Takano
发明人： Hirotaka Hara , Hiroyuki Hamasaki , Mitsuhiro Saeki , Kazuhiro Hirade , Makoto Takano
IPC分类号： G06F13/14 , G06F13/36
CPC分类号： G06T11/203 , G06T1/20
摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
摘要翻译：本发明的一个目的是提高图形数据处理器中用于绘制和显示控制的控制信息，图形数据等的传送效率。图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。

2. 发明申请

US20050030311A1 Data processor and graphic data processing device 有权
标题翻译：数据处理器和图形数据处理设备
公开(公告)号：US20050030311A1
公开(公告)日：2005-02-10
申请号：US10891047
申请日：2004-07-15
申请人： Hirotaka Hara , Hiroyuki Hamasaki , Mitsuhiro Saeki , Kazuhiro Hirade , Makoto Takano
发明人： Hirotaka Hara , Hiroyuki Hamasaki , Mitsuhiro Saeki , Kazuhiro Hirade , Makoto Takano
IPC分类号： G06F13/28 , G06F15/78 , G06T1/20 , G06T11/20 , G06T11/40 , G06T15/00 , G06T1/00 , G06F13/14
CPC分类号： G06T11/203 , G06T1/20
摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
摘要翻译：本发明的一个目的是提高图形数据处理器中绘图和显示控制的控制信息，图形数据等的传送效率。图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。

3. 发明申请

US20090015590A1 DATA PROCESSOR AND GRAPHIC DATA PROCESSING DEVICE 有权
标题翻译：数据处理器和图形数据处理设备
公开(公告)号：US20090015590A1
公开(公告)日：2009-01-15
申请号：US12237112
申请日：2008-09-24
申请人： HIROTAKA HARA , Hiroyuki Hamasaki , Mitsuhiro Saeki , Kazuhiro Hirade , Makoto Takano
发明人： HIROTAKA HARA , Hiroyuki Hamasaki , Mitsuhiro Saeki , Kazuhiro Hirade , Makoto Takano
IPC分类号： G06T15/00
CPC分类号： G06T11/203 , G06T1/20
摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
摘要翻译：本发明的一个目的是提高图形数据处理器中绘图和显示控制的控制信息，图形数据等的传送效率。图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。

4. 发明授权

US07446775B2 Data processor and graphic data processing device 有权
标题翻译：数据处理器和图形数据处理设备
公开(公告)号：US07446775B2
公开(公告)日：2008-11-04
申请号：US10891047
申请日：2004-07-15
申请人： Hirotaka Hara , Hiroyuki Hamasaki , Mitsuhiro Saeki , Kazuhiro Hirade , Makoto Takano
发明人： Hirotaka Hara , Hiroyuki Hamasaki , Mitsuhiro Saeki , Kazuhiro Hirade , Makoto Takano
IPC分类号： G06F13/14 , G06F13/36
CPC分类号： G06T11/203 , G06T1/20
摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
摘要翻译：本发明的一个目的是提高图形数据处理器中绘图和显示控制的控制信息，图形数据等的传送效率。图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。

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