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1. 发明申请

US20090059646A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20090059646A1
公开(公告)日：2009-03-05
申请号：US11912184
申请日：2006-04-13
申请人： Mitsue Takahashi , Shigeki Sakai
发明人： Mitsue Takahashi , Shigeki Sakai
IPC分类号： G11C11/22 , H01L29/78 , H01L27/115 , G11C7/00 , G11C11/34
CPC分类号： G11C11/22 , G11C11/223 , H01L21/28291 , H01L27/105 , H01L27/1159 , H01L27/11592
摘要： A field-effect transistor for nonvolatile memory holding use and a field-effect transistor for logical operation use are manufactured in the same structure on the same semiconductor substrate without separately providing manufacturing processes for the field-effect transistors for the two uses. Both a memory circuit and a logic circuit of a semiconductor integrated circuit are composed of n-channel and p-channel field-effect transistors including a memory holding material in a gate insulating structure. A logical operation state, a memory writing state and a nonvolatile memory holding state are electrically switched by controlling the level and application timing of a voltage to be applied between a gate conductor and a substrate region of the n-channel and p-channel field-effect transistors including the memory holding material in the gate insulating structure.
摘要翻译：在相同的半导体衬底上制造用于非易失性存储器保持用的场效应晶体管和用于逻辑运算使用的场效应晶体管，而不需要为这两种用途的场效应晶体管分别提供制造工艺。存储电路和半导体集成电路的逻辑电路都由包括栅极绝缘结构中的存储器保持材料的n沟道场效应晶体管和p沟道场效应晶体管构成。通过控制在n沟道和p沟道场效应晶体管的栅极导体和衬底区域之间施加的电压的电平和施加定时来电逻辑运行状态，存储器写入状态和非易失性存储器保持状态，包括存储器保持材料在栅极绝缘结构中的效应晶体管。

2. 发明授权

US08081499B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08081499B2
公开(公告)日：2011-12-20
申请号：US11912184
申请日：2006-04-13
申请人： Mitsue Takahashi , Shigeki Sakai
发明人： Mitsue Takahashi , Shigeki Sakai
IPC分类号： G11C11/22 , G11C11/24
CPC分类号： G11C11/22 , G11C11/223 , H01L21/28291 , H01L27/105 , H01L27/1159 , H01L27/11592
摘要： A field-effect transistor for nonvolatile memory holding use and a field-effect transistor for logical operation use are manufactured in the same structure on the same semiconductor substrate without separately providing manufacturing processes for the field-effect transistors for the two uses. Both a memory circuit and a logic circuit of a semiconductor integrated circuit are composed of n-channel and p-channel field-effect transistors including a memory holding material in a gate insulating structure. A logical operation state, a memory writing state and a nonvolatile memory holding state are electrically switched by controlling the level and application timing of a voltage to be applied between a gate conductor and a substrate region of the n-channel and p-channel field-effect transistors including the memory holding material in the gate insulating structure.
摘要翻译：在相同的半导体衬底上制造用于非易失性存储器保持用的场效应晶体管和用于逻辑运算使用的场效应晶体管，而不需要为这两种用途的场效应晶体管分别提供制造工艺。存储电路和半导体集成电路的逻辑电路都由包括栅极绝缘结构中的存储器保持材料的n沟道场效应晶体管和p沟道场效应晶体管构成。通过控制在n沟道和p沟道场效应晶体管的栅极导体和衬底区域之间施加的电压的电平和施加定时来电逻辑运行状态，存储器写入状态和非易失性存储器保持状态，包括存储器保持材料在栅极绝缘结构中的效应晶体管。

3. 发明申请

US20110038201A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20110038201A1
公开(公告)日：2011-02-17
申请号：US12513750
申请日：2007-10-29
申请人： Mitsue Takahashi , Shigeki Sakai
发明人： Mitsue Takahashi , Shigeki Sakai
IPC分类号： G11C11/4197 , G11C11/40
CPC分类号： H03K19/0185 , G11C11/22 , G11C11/223 , G11C14/00 , H01L21/28291 , H01L27/105 , H01L27/11585 , H01L27/1159 , H01L27/11592 , H01L29/78391
摘要： There is provided a semiconductor integrated circuit including a state detection enhancement circuit which includes an input terminal and an output terminal and has a function of generating an electric potential of a magnitude capable of performing nonvolatile memory writing into a nonvolatile memory circuit based on an electric potential input to the input terminal and outputting the electric potential of the magnitude to the output terminal, and the nonvolatile memory circuit has a nonvolatile memory function and an input terminal of the nonvolatile memory circuit is connected to the output of the state detection enhancement circuit. The state detection enhancement circuit is a positive or negative logical state detection enhancement circuit which includes a control signal terminal and a switch circuit which is turned on or off by a control signal applied to the control signal terminal, and has a function of either applying an output potential of the same logical state as or an inverse logical state of an input potential applied to the input terminal to the output terminal or completely breaking off a correlation between the input potential and the output potential when the switch circuit is in an OFF state, and has a function of applying an output potential which has the same logical state as or an inverse logical state of the input potential and has a larger highest-lowest potential range including a possible highest-lowest potential range of the input potential to the output terminal when the switch is in an ON state.
摘要翻译：提供了一种包括状态检测增强电路的半导体集成电路，其包括输入端子和输出端子，并且具有基于电位产生能够进行非易失性存储器写入非易失性存储器电路的幅度的电位的功能输入到输入端子并将大小的电位输出到输出端子，非易失性存储器电路具有非易失性存储功能，并且非易失性存储器电路的输入端子连接到状态检测增强电路的输出端。状态检测增强电路是正或负逻辑状态检测增强电路，其包括控制信号端子和通过施加到控制信号端子的控制信号而导通或截止的开关电路，并且具有应用与输入端子施加到输出端子的输入电位相同的逻辑状态的输出电位或反逻辑状态，或者当开关电路处于OFF状态时完全中断输入电位与输出电位之间的相关性，并且具有施加与输入电位具有相同逻辑状态或相反逻辑状态的输出电位的功能，并且具有包括输入电位的可能最高最低电位范围的较大最高 - 最低电位范围到输出端当开关处于ON状态时。

4. 发明授权

US06445633B2 Read amplifier circuit for high-speed reading and semiconductor memory device employing the read amplifier circuit 失效
标题翻译：用于高速读取的读取放大器电路和采用读取放大器电路的半导体存储器件
公开(公告)号：US06445633B2
公开(公告)日：2002-09-03
申请号：US09791772
申请日：2001-02-26
申请人： Mitsue Takahashi , Hiroaki Tanizaki
发明人： Mitsue Takahashi , Hiroaki Tanizaki
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C7/12 , G11C7/18 , G11C2207/002 , G11C2207/005
摘要： A read amplifier circuit includes an equalize start circuit. Based on a preamp enable signal PAE and an equalize signal IOEQ, the equalize start circuit generates an equalize start signal EQ for starting equalization at the timing when the preamp enable signal PAE is activated. Simultaneously with activation of a preamplifier by the preamp enable signal PAE, a pair of read lines GIOR and /GIOR is cut off from the preamplifier, and a P channel MOS transistor starts equalization of the pair of read lines GIOR and /GIOR. In this way, it is possible to start equalization of the paired read lines at the same time that the output signal is supplied to the preamplifier.
摘要翻译：读取放大器电路包括均衡启动电路。基于前置放大器使能信号PAE和均衡信号IOEQ，均衡启动电路在前置放大器使能信号PAE被激活的定时产生用于开始均衡的均衡启动信号EQ。在通过前置放大器使能信号PAE激活前置放大器的同时，从前置放大器切断一对读取线GIOR和/ GIOR，并且P沟道MOS晶体管开始对一对读取线GIOR和/ GIOR的均衡。以这种方式，可以在将输出信号提供给前置放大器的同时开始成对的读取行的均衡。

5. 发明授权

US08139388B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08139388B2
公开(公告)日：2012-03-20
申请号：US12565477
申请日：2009-09-23
申请人： Mitsue Takahashi , Shigeki Sakai , Shouyu Wang , Ken Takeuchi
发明人： Mitsue Takahashi , Shigeki Sakai , Shouyu Wang , Ken Takeuchi
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/223 , G11C11/5657
摘要： This invention has the purpose of providing a nonvolatile semiconductor storage device which is capable of entering multivalued storage in a FeFET unit without requiring preparation of a plurality of voltage sources.The nonvolatile semiconductor storage device is provided with multivalued ferroelectric memory cells which impart varied quantities of polarization to a ferroelectric material by applying pulse voltages having one and the same height and varied widths and consequently produce varied states of storage in conformity with the varied quantities of polarization.
摘要翻译：本发明的目的是提供一种能够在不需要准备多个电压源的情况下在FeFET单元中进入多值存储的非易失性半导体存储装置。非易失性半导体存储装置设置有多值铁电存储单元，其通过施加具有一个相同的高度和变化的宽度的脉冲电压而向铁电体材料施加不同数量的极化，并因此根据偏振极化量产生不同的存储状态。

6. 发明申请

US20100073988A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100073988A1
公开(公告)日：2010-03-25
申请号：US12565477
申请日：2009-09-23
申请人： Mitsue TAKAHASHI , Shigeki Sakai , Shouyu Wang , Ken Takeuchi
发明人： Mitsue TAKAHASHI , Shigeki Sakai , Shouyu Wang , Ken Takeuchi
IPC分类号： G11C11/22 , G11C8/00
CPC分类号： G11C11/22 , G11C11/223 , G11C11/5657
摘要： This invention has the purpose of providing a nonvolatile semiconductor storage device which is capable of entering multivalued storage in a FeFET unit without requiring preparation of a plurality of voltage sources.The nonvolatile semiconductor storage device is provided with multivalued ferroelectric memory cells which impart varied quantities of polarization to a ferroelectric material by applying pulse voltages having one and the same height and varied widths and consequently produce varied states of storage in conformity with the varied quantities of polarization.
摘要翻译：本发明的目的是提供一种能够在不需要准备多个电压源的情况下在FeFET单元中进入多值存储的非易失性半导体存储装置。非易失性半导体存储装置设置有多值铁电存储单元，其通过施加具有一个相同的高度和变化的宽度的脉冲电压而向铁电体材料施加不同数量的极化，并因此根据偏振极化量产生不同的存储状态。

7. 发明授权

US08159873B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08159873B2
公开(公告)日：2012-04-17
申请号：US12513750
申请日：2007-10-29
申请人： Mitsue Takahashi , Shigeki Sakai
发明人： Mitsue Takahashi , Shigeki Sakai
IPC分类号： G11C11/34
CPC分类号： H03K19/0185 , G11C11/22 , G11C11/223 , G11C14/00 , H01L21/28291 , H01L27/105 , H01L27/11585 , H01L27/1159 , H01L27/11592 , H01L29/78391
摘要： There is provided a semiconductor integrated circuit including a state detection enhancement circuit which includes an input terminal and an output terminal and has a function of generating an electric potential of a magnitude capable of performing nonvolatile memory writing into a nonvolatile memory circuit based on an electric potential input to the input terminal and outputting the electric potential of the magnitude to the output terminal, and the nonvolatile memory circuit has a nonvolatile memory function and an input terminal of the nonvolatile memory circuit is connected to the output of the state detection enhancement circuit. The state detection enhancement circuit is a positive or negative logical state detection enhancement circuit which includes a control signal terminal and a switch circuit which is turned on or off by a control signal applied to the control signal terminal, and has a function of either applying an output potential of the same logical state as or an inverse logical state of an input potential applied to the input terminal to the output terminal or completely breaking off a correlation between the input potential and the output potential when the switch circuit is in an OFF state, and has a function of applying an output potential which has the same logical state as or an inverse logical state of the input potential and has a larger highest-lowest potential range including a possible highest-lowest potential range of the input potential to the output terminal when the switch is in an ON state.
摘要翻译：提供了一种包括状态检测增强电路的半导体集成电路，其包括输入端子和输出端子，并且具有基于电位产生能够进行非易失性存储器写入非易失性存储器电路的幅度的电位的功能输入到输入端子并将大小的电位输出到输出端子，非易失性存储器电路具有非易失性存储功能，并且非易失性存储器电路的输入端子连接到状态检测增强电路的输出端。状态检测增强电路是正或负逻辑状态检测增强电路，其包括控制信号端子和通过施加到控制信号端子的控制信号而导通或截止的开关电路，并且具有应用与输入端子施加到输出端子的输入电位相同的逻辑状态的输出电位或反逻辑状态，或者当开关电路处于OFF状态时完全中断输入电位与输出电位之间的相关性，并且具有施加与输入电位具有相同逻辑状态或相反逻辑状态的输出电位的功能，并且具有包括输入电位的可能最高最低电位范围的较大最高 - 最低电位范围到输出端当开关处于ON状态时。

8. 发明授权

US6084386A Voltage generation circuit capable of supplying stable power supply voltage to load operating in response to timing signal 失效
标题翻译：电压产生电路能够提供稳定的电源电压以响应于定时信号而工作
公开(公告)号：US6084386A
公开(公告)日：2000-07-04
申请号：US362665
申请日：1999-07-29
申请人： Mitsue Takahashi , Tadaaki Yamauchi , Mitsuya Kinoshita
发明人： Mitsue Takahashi , Tadaaki Yamauchi , Mitsuya Kinoshita
IPC分类号： G11C11/413 , G05F1/565 , G11C11/407 , H02M3/137 , G05F1/40 , G05F1/56
CPC分类号： G05F1/565
摘要： A voltage generation circuit includes a voltage comparing circuit to compare a reference voltage signal Vi and an internal power supply voltage Vcc and a current supply transistor to supply current based on the output voltage of the voltage comparing circuit and maintain Vcc. The voltage generation circuit also includes a reference voltage signal generation circuit which responds to a control signal ACT activated for a prescribed time period prior to the operation timing of a load and sets Vi=Vref when control signal ACT is inactive and Vi=Vref+.DELTA.V when control signal ACT is active.
摘要翻译：电压产生电路包括用于比较参考电压信号Vi和内部电源电压Vcc的电压比较电路和电流源晶体管，以基于电压比较电路的输出电压提供电流并维持Vcc。电压产生电路还包括参考电压信号产生电路，其响应于在负载的操作定时之前的规定时间段内激活的控制信号ACT，并且当控制信号ACT无效时设置Vi = Vref，并且Vi = Vref + DELTA V 当控制信号ACT有效时。

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