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1. 发明授权

US08252377B2 Organoruthenium compound for use in chemical vapor deposition and chemical vapor deposition using the same 有权
标题翻译：用于化学气相沉积和使用其的化学气相沉积的有机钌化合物
公开(公告)号：US08252377B2
公开(公告)日：2012-08-28
申请号：US13182720
申请日：2011-07-14
申请人： Junichi Taniuchi , Masayuki Saito , Minoru Ishida
发明人： Junichi Taniuchi , Masayuki Saito , Minoru Ishida
IPC分类号： C23C16/18
CPC分类号： C07F15/0046 , C07F17/02 , C23C16/18 , H01L21/28556
摘要： The present invention is an organoruthenium compound for use in production of a ruthenium or ruthenium compound thin film by chemical vapor deposition, including ruthenium and an arene group and norbornadiene both coordinated to the ruthenium and represented by the following formula. The present invention is an organoruthenium compound for use in chemical vapor deposition which does not require the coexistence of oxygen during the thin film formation, and moreover, is liquid at ordinary temperature, thereby having good handleability and recyclability. wherein the substituents, R1 to R6, of the arene group are each hydrogen or an alkyl group, and the total number of carbons of R1 to R6 (R1+R2+R3+R4+R5+R6) is 6 or less.
摘要翻译：本发明是用于通过化学气相沉积制造钌或钌化合物薄膜的有机钌化合物，包括钌和芳族基团和降冰片二烯，二者均与钌配位并由下式表示。本发明是用于化学气相沉积的有机钌化合物，其在薄膜形成期间不需要氧的共存，而且在常温下为液体，因此具有良好的可操作性和可回收性。其中芳基的取代基R 1〜R 6各自为氢或烷基，R 1〜R 6（R 1 + R 2 + R 3 + R 4 + R 5 + R 6）的碳原子数为6以下。

2. 发明申请

US20110234852A1 Imaging apparatus, image processing apparatus, image processing method, and program 有权
标题翻译：成像装置，图像处理装置，图像处理方法和程序
公开(公告)号：US20110234852A1
公开(公告)日：2011-09-29
申请号：US12929984
申请日：2011-03-01
申请人： Minoru Ishida
发明人： Minoru Ishida
IPC分类号： H04N5/225
CPC分类号： H04N5/23238 , H04M2250/52 , H04N5/225
摘要： An imaging apparatus includes: an image generation section that generates at least one of a first captured image having a predetermined size and a second captured image having an aspect ratio different from that of the first captured image; a recording control section that, when an instruction operation to record the generated captured image is received, records the generated captured image based on the instruction operation; and a display control section that, when a captured image to be displayed at the time of displaying the recorded captured image on a display section is the second captured image, displays the second captured image and an enlarged image of a specific region in the second captured image are displayed on the display section in a correlated manner.
摘要翻译：一种成像装置包括：图像生成部，其生成具有预定尺寸的第一拍摄图像和具有与第一拍摄图像的纵横比不同的纵横比的第二拍摄图像中的至少一个; 记录控制部分，当接收到记录所生成的拍摄图像的指令操作时，基于指令操作记录生成的拍摄图像; 以及显示控制部，当在显示部上显示记录的拍摄图像时要显示的拍摄图像是第二拍摄图像时，在第二拍摄图像中显示第二拍摄图像和特定区域的放大图像图像以相关方式显示在显示部分上。

3. 发明申请

US20090238970A1 ORGANIC RUTHENIUM COMPOUND FOR CHEMICAL VAPOR DEPOSITION, AND CHEMICAL VAPOR DEPOSITION METHOD USING THE ORGANIC RUTHENIUM COMPOUND 有权
标题翻译：用于化学蒸气沉积的有机元素化合物和使用有机金属化合物的化学气相沉积方法
公开(公告)号：US20090238970A1
公开(公告)日：2009-09-24
申请号：US12091782
申请日：2007-09-27
申请人： Junichi Taniuchi , Masayuki Saito , Minoru Ishida
发明人： Junichi Taniuchi , Masayuki Saito , Minoru Ishida
IPC分类号： C23C16/06 , C07F17/02 , C23C16/18
CPC分类号： C07F15/0046 , C07F17/02 , C23C16/18 , H01L21/28556
摘要： The present invention is an organoruthenium compound for use in production of a ruthenium or ruthenium compound thin film by chemical vapor deposition, including ruthenium and an arene group and norbornadiene both coordinated to the ruthenium and represented by the following formula. The present invention is an organoruthenium compound for use in chemical vapor deposition which does not require the coexistence of oxygen during the thin film formation, and moreover, is liquid at ordinary temperature, thereby having good handleability and recyclability. wherein the substituents, R1 to R6, of the arene group are each hydrogen or an alkyl group, and the total number of carbons of R1 to R6 (R1+R2+R3+R4+R5+R6) is 6 or less.
摘要翻译：本发明是用于通过化学气相沉积制造钌或钌化合物薄膜的有机钌化合物，包括钌和芳族基团和降冰片二烯，二者均与钌配位并由下式表示。本发明是用于化学气相沉积的有机钌化合物，其在薄膜形成期间不需要氧的共存，而且在常温下为液体，因此具有良好的可操作性和可回收性。其中芳基的取代基R 1〜R 6各自为氢或烷基，R 1〜R 6（R 1 + R 2 + R 3 + R 4 + R 5 + R 6）的碳原子数为6以下。

4. 发明授权

US07574730B1 Device and system for reducing confluence noise 失效
标题翻译：减少汇流噪声的装置和系统
公开(公告)号：US07574730B1
公开(公告)日：2009-08-11
申请号：US09589142
申请日：2000-06-07
申请人： Shigefumi Masuda , Minoru Ishida
发明人： Shigefumi Masuda , Minoru Ishida
IPC分类号： H04N7/173
CPC分类号： H04L12/6418 , H04N7/102
摘要： A system for reducing noise in a signal line, through which upward signals and downward signals are transmitted between a center and terminals, includes a noise-reduction device provided between the center and the terminals. The noise-reduction device attenuates the upward signals by an increased amount when a noise increase regarding the upward signals is detected on the signal line. The system further includes a noise-control device, provided at terminals, which boosts a transmission level of the upward signals by an amount compensating for the attenuation of the upward signals by the noise-reduction device.
摘要翻译：一种用于降低信号线中的噪声的系统，通过其在中心和终端之间传输向上信号和向下信号，包括设置在中心和终端之间的降噪装置。当在信号线上检测到关于上行信号的噪声增加时，降噪装置衰减上升信号增加的量。该系统还包括设置在端子处的噪声控制装置，其通过减少由降噪装置对上行信号衰减的量来增加上行信号的发送电平。

5. 发明授权

US06953533B2 Process for removing chromide coatings from metal substrates, and related compositions 有权
标题翻译：用于从金属基底去除铬化物涂层的方法以及相关组合物
公开(公告)号：US06953533B2
公开(公告)日：2005-10-11
申请号：US10462049
申请日：2003-06-16
申请人： Lawrence Bernard Kool , Kenneth Burrell Potter , William Randall Thompson , David Carr , Kiyokazu Watanabe , Minoru Ishida , Kazuharu Hattori
发明人： Lawrence Bernard Kool , Kenneth Burrell Potter , William Randall Thompson , David Carr , Kiyokazu Watanabe , Minoru Ishida , Kazuharu Hattori
IPC分类号： C23F1/44 , C23G1/10 , F01D5/00 , B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00 , C25F3/00
CPC分类号： F01D5/005 , C23F1/16 , C23F1/26 , C23F1/44 , C23G1/10 , F05D2230/80 , F05D2230/90
摘要： A method for removing a chromide coating from the surface of a substrate is described. The coating is treated with a composition which includes an acid having the formula HxAF6, where “A” can be Si, Ge, Ti, Zr, Al, or Ga; and x is 1–6. An exemplary acid is hexafluorosilicic acid. The composition may also include a second acid, such as phosphoric acid or nitric acid. In some instances, a third acid is employed, such as hydrochloric acid. A related repair method for replacing a worn or damaged chromide coating is described. The coating is often applied to portions of turbine engine components made from superalloy materials.
摘要翻译：描述了从基板的表面去除铬化物涂层的方法。涂层用包括具有下式的酸组成的组合物处理：其中“A”可以是Si，Ge，Ti，Zr，Al或 Ga x为1-6。示例性的酸是六氟硅酸。组合物还可以包括第二种酸，如磷酸或硝酸。在一些情况下，使用第三种酸，例如盐酸。描述了用于替换磨损或损坏的铬酸盐涂层的相关修复方法。涂层通常用于由超级合金材料制成的涡轮发动机部件的部分。

6. 发明申请

US20050121697A1 Storage device 有权
标题翻译：储存设备
公开(公告)号：US20050121697A1
公开(公告)日：2005-06-09
申请号：US10999050
申请日：2004-11-29
申请人： Minoru Ishida , Katsuhisa Aratani , Akira Kouchiyama , Tomohito Tsushima
发明人： Minoru Ishida , Katsuhisa Aratani , Akira Kouchiyama , Tomohito Tsushima
IPC分类号： G11C16/04 , G11C13/02 , H01L27/10 , H01L31/109 , H01L45/00
CPC分类号： G11C13/0011 , G11C13/0009 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/34 , G11C2213/51 , G11C2213/56 , G11C2213/72 , G11C2213/79 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1266 , H01L45/144 , H01L45/146
摘要： A storage device includes a first electrode, a second electrode facing the first electrode, an inter-electrode material layer provided between the first electrode and the second electrode, and a voltage application unit applying a predetermined voltage to the first and the second electrodes. Furthermore, an oxidation-reduction active material changeable into an electrode reaction inhibition layer by applying voltages to the first and the second electrodes is contained in a region that is covered by an electric field, the electric field being generated when the voltage is applied, and the electrode reaction inhibition layer is either formed along an interface region between the second electrode and the inter-electrode material layer, or changes an area thereof, or disappears depending on an application condition of the voltage to the first and the second.
摘要翻译：存储装置包括第一电极，面对第一电极的第二电极，设置在第一电极和第二电极之间的电极间材料层，以及向第一和第二电极施加预定电压的电压施加单元。此外，通过向第一和第二电极施加电压而可变化为电极反应抑制层的氧化还原活性物质被包含在被电场覆盖的区域中，电场在施加电压时产生，并且电极反应抑制层沿着第二电极和电极间材料层之间的界面区域形成，或者改变其面积，或者根据第一和第二电压的施加条件而消失。

7. 发明授权

US06642555B1 Semiconductor memory device 有权
公开(公告)号：US06642555B1
公开(公告)日：2003-11-04
申请号：US09779813
申请日：2001-02-08
申请人： Minoru Ishida
发明人： Minoru Ishida
IPC分类号： H01L2710
CPC分类号： H01L27/11 , G11C11/412 , H01L27/1104
摘要： A semiconductor memory device provided with a plurality of memory cells each including first transistors having first conductivity type and second transistors having a second conductivity type, each memory cell comprising a first active region where channels of the first transistors are formed and a second active region where channels of the second transistors are formed, the first and second active regions being arranged so that the directions of channel currents of the transistors become parallel to each other in each cell and being separated between adjoining memory cells in a direction perpendicular to the directions of channel current.

8. 发明授权

US06525382B1 Semiconductor memory device and method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06525382B1
公开(公告)日：2003-02-25
申请号：US09570560
申请日：2000-05-12
申请人： Minoru Ishida
发明人： Minoru Ishida
IPC分类号： H01L2976
CPC分类号： H01L27/11 , H01L21/76895 , H01L27/0207 , H01L27/1104 , Y10S257/903
摘要： Provided are a semiconductor memory device and a method of manufacturing the same, in which landing pad layers in correspondence to contacts connecting to a power supply voltage line and a bit line can be easily formed in the same layer as node wiring, thereby simplifying the manufacturing process. Resist patterns having a roughly C shape i.e., patterns of two sets of node wiring are formed not in the same direction in all memory cells but in a different direction from each other between neighboring cells in up-down and right-left directions. Furthermore, out of four sides of each memory cell resist patterns i.e., patterns of the landing pad layer are formed on the two sides opposite the two sides close to the resist patterns for the two sets of node wiring. Accordingly, the landing pad layers can be formed in the same layer as the node wiring, the landing pad layers corresponding to contacts connecting to a grounded line, power supply voltage line and bit line in the upper layer from the node wiring.
摘要翻译：提供一种半导体存储器件及其制造方法，其中可以容易地在与节点布线相同的层中形成与连接到电源电压线和位线的触点对应的着陆焊盘层，从而简化制造处理。具有大致C形的抵抗图案，即两组节点布线的图案在所有存储单元中形成为不是相同的方向，而是在上下左右方向上在相邻单元之间彼此不同的方向上形成。此外，在每个存储单元的四个侧面中，抵抗图案，即，在靠近两组节点布线的抗蚀剂图案的两侧相对的两侧上形成着陆焊盘层的图案。因此，着陆焊盘层可以形成在与节点布线相同的层中，着陆焊盘层对应于从节点布线连接到上层的接地线，电源电压线和位线。

9. 发明授权

US06476424B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06476424B1
公开(公告)日：2002-11-05
申请号：US09499612
申请日：2000-02-07
申请人： Minoru Ishida
发明人： Minoru Ishida
IPC分类号： H01L2710
CPC分类号： H01L27/1104 , H01L27/0207 , Y10S257/903
摘要： A semiconductor memory device which can suppress the occurrence of corner rounding through the resist patterning process to achieve a reduction in cell size and higher integration. A relationship between a channel width DT.W of the drive transistor, a channel length DT.L of the drive transistor, a channel width WT.W of the word transistor and a channel length WT.L of the word transistor is given by: (DT.W/WT.W)/(WT.L/DT.L) 1.
摘要翻译：一种半导体存储器件，其可以通过抗蚀剂图案化工艺抑制拐角圆角的发生，以实现电池尺寸的减小和更高的集成度。驱动晶体管的沟道宽度DT.W，驱动晶体管的沟道长度DT.L，字晶体管的沟道宽度WT.W和字晶体管的沟道长度WT.L之间的关系由下式给出：（DT.W / WT.W）/（WT.L / DT.L）<1.2。驱动晶体管的沟道宽度DT.W等于字晶体管的沟道宽度WT.W，以减少p型有源区的图案中的步长。字晶体管的沟道长度WT.L大于驱动晶体管的沟道长度DT.L，即（WT.L / DT.L）> 1。

10. 发明授权

US6101120A Semiconductor memory device 有权
公开(公告)号：US6101120A
公开(公告)日：2000-08-08
申请号：US356364
申请日：1999-07-19
申请人： Minoru Ishida
发明人： Minoru Ishida
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/786 , G11C11/00
CPC分类号： G11C11/24 , H01L27/11 , H01L27/1104 , G11C11/5664 , G11C13/0014 , G11C13/0069 , Y10S257/903 , Y10S257/904
摘要： A semiconductor memory device which can reduce the size of a memory cell and increase the packing density is disclosed. Each memory cell comprises a p-type active region, an n-type active region, two word lines, a common gate line and a common gate line. Two memory cells are deviated by, for example, an amount of a half bit in the direction which perpendicularly crosses the word line direction. The memory cells are arranged with one of their parts overlapped with one another in the word line direction. Thus, the size of the memory cell can be reduced in the word line direction.

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