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1. 发明申请

US20100167491A1 METHOD FOR FABRICATING FLASH MEMORY DEVICE 审中-公开
标题翻译：用于制造闪速存储器件的方法
公开(公告)号：US20100167491A1
公开(公告)日：2010-07-01
申请号：US12637003
申请日：2009-12-14
申请人： Min-Gon Lee
发明人： Min-Gon Lee
IPC分类号： H01L21/76 , H01L21/28
CPC分类号： H01L27/11521
摘要： A method for fabricating a flash memory device includes forming device isolation films in a semiconductor substrate, defining active regions between the device isolation films, and patterning floating gates on the semiconductor substrate to correspond to the active regions. Portions where the active regions and the floating gates are not overlap with one another are within reference offset ranges, respectively.
摘要翻译：一种用于制造闪速存储器件的方法包括在半导体衬底中形成器件隔离膜，限定器件隔离膜之间的有源区，以及对半导体衬底上的浮动栅极进行构图，以对应于有源区。活动区域和浮动栅极彼此不重叠的部分分别在参考偏移范围内。

2. 发明申请

US20130170094A1 MULTILAYER CERAMIC CAPACITOR 有权
标题翻译：多层陶瓷电容器
公开(公告)号：US20130170094A1
公开(公告)日：2013-07-04
申请号：US13781286
申请日：2013-02-28
申请人： Sang Huk KIM , Hyung Joon KIM , Ju Myung SUH , Jang Ho LEE , Jun Hee KIM , Min Gon LEE
发明人： Sang Huk KIM , Hyung Joon KIM , Ju Myung SUH , Jang Ho LEE , Jun Hee KIM , Min Gon LEE
IPC分类号： H01G4/01 , H01G4/12
CPC分类号： H01G4/01 , H01G4/005 , H01G4/12 , H01G4/30
摘要： There is provided a multilayer ceramic capacitor, including: a multilayer body having a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated; wherein each internal electrode layer has a width gradually decreases from a center thereof towards both ends thereof in a length direction; and when a width of each internal electrode layer at the ends thereof in the length direction is defined as a minimum width L2 and a width of a portion of a margin portion M in each dielectric layer is defined as a maximum width M2, the portion of the margin portion M having no internal electrode layer present thereon and corresponding to the ends of each internal electrode layer in the length direction, a ratio of M2 to L2 (M2/L2) ranges from 0.2 to 0.3.
摘要翻译：提供了一种多层陶瓷电容器，其包括：具有交替层叠的多个电介质层和多个内部电极层的多层体; 其中每个内部电极层的宽度从长度方向的中心向其两端逐渐减小; 并且当将每个内部电极层在其长度方向上的端部的宽度定义为最小宽度L2，将每个电介质层中的边缘部分M的一部分的宽度定义为最大宽度M2时，边缘部M在其上不存在内部电极层，并且与长度方向上的每个内部电极层的端部相对应，M2与L2的比（M2 / L2）为0.2〜0.3。

3. 发明申请

US20090197388A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20090197388A1
公开(公告)日：2009-08-06
申请号：US11869452
申请日：2007-10-09
申请人： Min-Gon Lee
发明人： Min-Gon Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/823481
摘要： A method of manufacturing a semiconductor device including at leasty one of the following steps: sequentially forming a first oxide layer, a nitride layer, a second oxide layer, a bottom anti-reflect coating and a photo-resist pattern over a semiconductor substrate; exposing the uppermost surface of the semiconductor substrate by performing a first reactive ion etch process; and then forming a trench in the uppermost surface of the semiconductor substrate by performing a second reactive ion etch process.
摘要翻译：一种制造半导体器件的方法，包括至少一个以下步骤：在半导体衬底上顺序形成第一氧化物层，氮化物层，第二氧化物层，底部抗反射涂层和光刻胶图案; 通过执行第一反应离子蚀刻工艺暴露半导体衬底的最上表面; 然后通过执行第二反应离子蚀刻工艺在半导体衬底的最上表面中形成沟槽。

4. 发明申请

US20120307414A1 MULTILAYER CERAMIC CAPACITOR 有权
标题翻译：多层陶瓷电容器
公开(公告)号：US20120307414A1
公开(公告)日：2012-12-06
申请号：US13478540
申请日：2012-05-23
申请人： Sang Huk Kim , Hyung Joon Kim , Ju Myung Suh , Jang Ho Lee , Jun Hee Kim , Min Gon Lee
发明人： Sang Huk Kim , Hyung Joon Kim , Ju Myung Suh , Jang Ho Lee , Jun Hee Kim , Min Gon Lee
IPC分类号： H01G4/30
CPC分类号： H01G4/01 , H01G4/005 , H01G4/12 , H01G4/30
摘要： There is provided a multilayer ceramic capacitor, including: a multilayer body having a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated; wherein each internal electrode layer has a width gradually decreases from a center thereof towards both ends thereof in a length direction; and when a width of each internal electrode layer at the ends thereof in the length direction is defined as a minimum width L2 and a width of a portion of a margin portion M in each dielectric layer is defined as a maximum width M2, the portion of the margin portion M having no internal electrode layer present thereon and corresponding to the ends of each internal electrode layer in the length direction, a ratio of M2 to L2 (M2/L2) ranges from 0.2 to 0.3.
摘要翻译：提供了一种多层陶瓷电容器，其包括：具有交替层叠的多个电介质层和多个内部电极层的多层体; 其中每个内部电极层的宽度从长度方向的中心向其两端逐渐减小; 并且当将每个内部电极层在其长度方向上的端部的宽度定义为最小宽度L2，将每个电介质层中的边缘部分M的一部分的宽度定义为最大宽度M2时，边缘部M在其上不存在内部电极层，并且与长度方向上的每个内部电极层的端部相对应，M2与L2的比（M2 / L2）为0.2〜0.3。

5. 发明授权

US08400753B2 Multilayer ceramic capacitor 有权
标题翻译：多层陶瓷电容器
公开(公告)号：US08400753B2
公开(公告)日：2013-03-19
申请号：US13478540
申请日：2012-05-23
申请人： Sang Huk Kim , Hyung Joon Kim , Ju Myung Suh , Jang Ho Lee , Jun Hee Kim , Min Gon Lee
发明人： Sang Huk Kim , Hyung Joon Kim , Ju Myung Suh , Jang Ho Lee , Jun Hee Kim , Min Gon Lee
IPC分类号： H01G4/005
CPC分类号： H01G4/01 , H01G4/005 , H01G4/12 , H01G4/30
摘要： There is provided a multilayer ceramic capacitor, including: a multilayer body having a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated; wherein each internal electrode layer has a width gradually decreases from a center thereof towards both ends thereof in a length direction; and when a width of each internal electrode layer at the ends thereof in the length direction is defined as a minimum width L2 and a width of a portion of a margin portion M in each dielectric layer is defined as a maximum width M2, the portion of the margin portion M having no internal electrode layer present thereon and corresponding to the ends of each internal electrode layer in the length direction, a ratio of M2 to L2 (M2/L2) ranges from 0.2 to 0.3.
摘要翻译：提供了一种多层陶瓷电容器，其包括：具有交替层叠的多个电介质层和多个内部电极层的多层体; 其中每个内部电极层的宽度从长度方向的中心向其两端逐渐减小; 并且当将每个内部电极层在其长度方向上的端部的宽度定义为最小宽度L2，将每个电介质层中的边缘部分M的一部分的宽度定义为最大宽度M2时，边缘部M在其上不存在内部电极层，并且与长度方向上的每个内部电极层的端部相对应，M2与L2的比（M2 / L2）为0.2〜0.3。

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