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    • 1. 发明授权
    • 3D chip arrangement including memory manager
    • 3D芯片布置包括内存管理器
    • US07894229B2
    • 2011-02-22
    • US12343223
    • 2008-12-23
    • Vesa LahtinenTapio HillKimmo KuusilinnaJari NikaraMika KuulusaTommi Makelainen
    • Vesa LahtinenTapio HillKimmo KuusilinnaJari NikaraMika KuulusaTommi Makelainen
    • G11C5/02
    • G11C5/025G11C5/02H01L25/0652H01L25/18H01L2224/13025H01L2224/16145H01L2224/16225H01L2224/17181H01L2225/06513H01L2225/06517H01L2225/06541H01L2924/00011H01L2924/00014H01L2924/15311H01L2224/0401
    • Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface connecting the memory management unit with the at least one logic die, a second data interface connecting the memory management unit with the at least one memory die, a configuration interface connecting the memory management unit with the at least one memory die, where the configuration interface includes face-to-face connections, a control interface connecting the memory management unit with the at least one logic die, where the memory die(s) and the logic die(s) are arranged in a stacked configuration on the base substrate, and the memory management unit is adapted for managing memory accesses from the subsystem(s) by negotiating an allowed memory access with the subsystem(s) via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface.
    • 涉及集中式存储器管理的系统,装置和方法能够动态分配和分配所有子系统的存储器。 一个实施例涉及基底基板,基底基板上的逻辑管芯,并具有子系统,具有存储器模块的存储管芯,存储器管理单元,第一数据接口,其将 具有所述至少一个逻辑管芯的存储器管理单元,将所述存储器管理单元与所述至少一个存储管芯连接的第二数据接口,将所述存储器管理单元与所述至少一个存储器管芯连接的配置接口,其中所述配置接口包括面 面对连接,将存储器管理单元与至少一个逻辑管芯连接的控制接口,其中存储器管芯和逻辑管芯以堆叠配置布置在基底衬底上,并且存储器 管理单元适于通过经由所述控制接口协商与所述子系统的允许的存储器访问来管理来自所述子系统的存储器访问,并且根据所述允许的存储器访问vi来配置所述至少一个存储器模块 一个配置界面。
    • 4. 发明申请
    • 3D CHIP ARRANGEMENT INCLUDING MEMORY MANAGER
    • 3D芯片安排,包括内存管理器
    • US20090147557A1
    • 2009-06-11
    • US12343223
    • 2008-12-23
    • VESA LAHTINENTAPIO HILLKIMMO KUUSILINNAJARI NIKARAMIKA KUULUSATOMMI MAKELAINEN
    • VESA LAHTINENTAPIO HILLKIMMO KUUSILINNAJARI NIKARAMIKA KUULUSATOMMI MAKELAINEN
    • G11C5/02G11C5/06
    • G11C5/025G11C5/02H01L25/0652H01L25/18H01L2224/13025H01L2224/16145H01L2224/16225H01L2224/17181H01L2225/06513H01L2225/06517H01L2225/06541H01L2924/00011H01L2924/00014H01L2924/15311H01L2224/0401
    • Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface connecting the memory management unit with the at least one logic die, a second data interface connecting the memory management unit with the at least one memory die, a configuration interface connecting the memory management unit with the at least one memory die, where the configuration interface includes face-to-face connections, a control interface connecting the memory management unit with the at least one logic die, where the memory die(s) and the logic die(s) are arranged in a stacked configuration on the base substrate, and the memory management unit is adapted for managing memory accesses from the subsystem(s) by negotiating an allowed memory access with the subsystem(s) via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface.
    • 涉及集中式存储器管理的系统,装置和方法能够动态分配和分配所有子系统的存储器。 一个实施例涉及基底基板,基底基板上的逻辑管芯,并具有子系统,具有存储器模块的存储管芯,存储器管理单元,第一数据接口,其将 具有所述至少一个逻辑管芯的存储器管理单元,将所述存储器管理单元与所述至少一个存储管芯连接的第二数据接口,将所述存储器管理单元与所述至少一个存储器管芯连接的配置接口,其中所述配置接口包括面 面对连接,将存储器管理单元与至少一个逻辑管芯连接的控制接口,其中存储器管芯和逻辑管芯以堆叠配置布置在基底衬底上,并且存储器 管理单元适于通过经由所述控制接口协商与所述子系统的允许的存储器访问来管理来自所述子系统的存储器访问,并且根据所述允许的存储器访问vi来配置所述至少一个存储器模块 一个配置界面。
    • 5. 发明授权
    • 3D chip arrangement including memory manager
    • 3D芯片布置包括内存管理器
    • US07477535B2
    • 2009-01-13
    • US11543351
    • 2006-10-05
    • Vesa LahtinenTapio HillKimmo KuusilinnaJari NikaraMika KuulusaTommi Makelainen
    • Vesa LahtinenTapio HillKimmo KuusilinnaJari NikaraMika KuulusaTommi Makelainen
    • G11C5/02
    • G11C5/025G11C5/02H01L25/0652H01L25/18H01L2224/13025H01L2224/16145H01L2224/16225H01L2224/17181H01L2225/06513H01L2225/06517H01L2225/06541H01L2924/00011H01L2924/00014H01L2924/15311H01L2224/0401
    • Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface connecting the memory management unit with the at least one logic die, a second data interface connecting the memory management unit with the at least one memory die, a configuration interface connecting the memory management unit with the at least one memory die, where the configuration interface includes face-to-face connections, a control interface connecting the memory management unit with the at least one logic die, where the memory die(s) and the logic die(s) are arranged in a stacked configuration on the base substrate, and the memory management unit is adapted for managing memory accesses from the subsystem(s) by negotiating an allowed memory access with the subsystem(s) via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface.
    • 涉及集中式存储器管理的系统,装置和方法能够动态分配和分配所有子系统的存储器。 一个实施例涉及基底基板,基底基板上的逻辑管芯,并具有子系统,具有存储器模块的存储管芯,存储器管理单元,第一数据接口,其将 具有所述至少一个逻辑管芯的存储器管理单元,将所述存储器管理单元与所述至少一个存储管芯连接的第二数据接口,将所述存储器管理单元与所述至少一个存储器管芯连接的配置接口,其中所述配置接口包括面 面对连接,将存储器管理单元与至少一个逻辑管芯连接的控制接口,其中存储器管芯和逻辑管芯以堆叠配置布置在基底衬底上,并且存储器 管理单元适于通过经由所述控制接口协商与所述子系统的允许的存储器访问来管理来自所述子系统的存储器访问,并且根据所述允许的存储器访问vi来配置所述至少一个存储器模块 一个配置界面。
    • 6. 发明申请
    • METHOD AND APPARATUS FOR PROVIDING DETAILED PROGRESS INDICATORS
    • 提供详细进度指标的方法和装置
    • US20120304098A1
    • 2012-11-29
    • US13117856
    • 2011-05-27
    • Mika Kuulusa
    • Mika Kuulusa
    • G06F3/048
    • G06F3/0481G06Q10/103G06Q30/0207G06Q50/01
    • An approach is provided for providing detailed progress indicators. A progress indicator platform determines a plurality of entities associated with performing at least one task. The progress indicator platform determines progress information for performing the at least one task. Nest, the progress indicator platform processes and/or facilitates a processing of the progress information to determine task contribution information associated with respective ones of the plurality of entities. Next, the progress indicator platform causes, at least in part, a rendering of a user interface element to depict, at least in part, the progress information, the task contribution information, or a combination thereof.
    • 提供了一种提供详细进度指标的方法。 进度指示器平台确定与执行至少一个任务相关联的多个实体。 进度指示器平台确定用于执行至少一个任务的进度信息。 Nest,进度指示器平台处理和/或促进进度信息的处理以确定与多个实体中的相应实体相关联的任务贡献信息。 接下来,进度指示器平台至少部分地导致用户界面元素的呈现至少部分地描绘进度信息,任务贡献信息或其组合。
    • 8. 发明申请
    • 3D chip arrangement including memory manager
    • 3D芯片布置包括内存管理器
    • US20080084725A1
    • 2008-04-10
    • US11543351
    • 2006-10-05
    • Vesa LahtinenTapio HillKimmo KuusilinnaJari NikaraMika KuulusaTommi Makelainen
    • Vesa LahtinenTapio HillKimmo KuusilinnaJari NikaraMika KuulusaTommi Makelainen
    • G11C5/02G06F15/177G06F9/24G06F9/00
    • G11C5/025G11C5/02H01L25/0652H01L25/18H01L2224/13025H01L2224/16145H01L2224/16225H01L2224/17181H01L2225/06513H01L2225/06517H01L2225/06541H01L2924/00011H01L2924/00014H01L2924/15311H01L2224/0401
    • Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface connecting the memory management unit with the at least one logic die, a second data interface connecting the memory management unit with the at least one memory die, a configuration interface connecting the memory management unit with the at least one memory die, where the configuration interface includes face-to-face connections, a control interface connecting the memory management unit with the at least one logic die, where the memory die(s) and the logic die(s) are arranged in a stacked configuration on the base substrate, and the memory management unit is adapted for managing memory accesses from the subsystem(s) by negotiating an allowed memory access with the subsystem(s) via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface.
    • 涉及集中式存储器管理的系统,装置和方法能够动态分配和分配所有子系统的存储器。 一个实施例涉及基底基板,基底基板上的逻辑管芯,并具有子系统,具有存储器模块的存储管芯,存储器管理单元,第一数据接口,其将 具有所述至少一个逻辑管芯的存储器管理单元,将所述存储器管理单元与所述至少一个存储管芯连接的第二数据接口,将所述存储器管理单元与所述至少一个存储器管芯连接的配置接口,其中所述配置接口包括面 面对连接,将存储器管理单元与至少一个逻辑管芯连接的控制接口,其中存储器管芯和逻辑管芯以堆叠配置布置在基底衬底上,并且存储器 管理单元适于通过经由所述控制接口协商与所述子系统的允许的存储器访问来管理来自所述子系统的存储器访问,并且根据所述允许的存储器访问vi来配置所述至少一个存储器模块 一个配置界面。