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1. 发明申请

US20180219641A1 FRACTIONAL MULTIPLEXING OF SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE LINKS 审中-公开
公开(公告)号：US20180219641A1
公开(公告)日：2018-08-02
申请号：US15418201
申请日：2017-01-27
申请人： Microsemi Storage Solutions (U.S.), Inc.
发明人： Gregory Arthur TABOR , John Matthew ADAMS , Keith Graham SHAW , Larrie Simon CARR , Salman GHUFRAN
IPC分类号： H04J3/16 , H04L12/863
CPC分类号： H04J3/1694 , H04L47/623
摘要： Methods, devices, and systems relating to Serial Attached SCSI (SAS) storage interconnect technology are provided. An SAS serial connection is established between an SAS initiator and an SAS expander over a physical link for communications between the SAS initiator and a plurality of target devices. The plurality of target devices is in communication with the SAS expander. SAS packets associated with each of the plurality of target devices are dynamically multiplexed and transmitted over the single SAS serial connection. Each SAS packet comprises one or more information bits indicating the target device with which the SAS packet is associated. The dynamically multiplexed SAS packets transmitted over the SAS connection may comprise SAS packets associated with at least two target devices having different maximum physical link rates. A result may be improved bandwidth utilization of the physical link when legacy SAS target devices with slower physical link rates are utilized.

2. 发明申请

US20170249969A1 METHOD AND SYSTEM FOR HANDLING RANDOM ACCESS WRITE REQUESTS FOR A SHINGLED MAGNETIC RECORDING HARD DISK DRIVE 审中-公开
公开(公告)号：US20170249969A1
公开(公告)日：2017-08-31
申请号：US15387164
申请日：2016-12-21
申请人： Microsemi Storage Solutions (U.S.), Inc.
发明人： Anthony Frank AIELLO , Robert CALDWELL
IPC分类号： G11B20/12 , G06F3/06 , G06F12/0802 , G06F12/02
CPC分类号： G11B20/1217 , G06F3/061 , G06F3/0647 , G06F3/0656 , G06F3/0665 , G06F3/0673 , G06F11/1076 , G06F12/0253 , G06F12/0802 , G06F12/0866 , G06F2212/262 , G06F2212/60 , G06F2212/7205 , G11B2020/10916
摘要： Methods, devices and systems are provided for making a shingled magnetic recording (SMR) hard disk drive operate with similar random access characteristics of a conventional hard drive despite the SMR disk having strict sequential write requirements. A virtual space manager manages a virtual address space, which is visible to a host system, and maps virtual addresses to logical addresses on the SMR disk. A logical space manager controls the placement of data on the SMR disk and ensures that writes to the disk comply with the sequential write requirements. The disk is subdivided into a plurality of stripes each comprising one or more blocks. When a block located within a stripe is to be rewritten with new data, the entire stripe is read from the SMR disk into a memory of the system, the stripe is modified in the memory to replace the previous data stored in the block with the new data, and the modified stripe is written to a new, next available stripe on the disk.

3. 发明申请

US20170235864A1 METHODS AND SYSTEMS FOR FUNCTIONAL ANALYSIS OF AN INTEGRATED CIRCUIT 审中-公开
公开(公告)号：US20170235864A1
公开(公告)日：2017-08-17
申请号：US15583316
申请日：2017-05-01
申请人： MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
发明人： Theodore WILSON
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505 , G06F2217/62 , G06F2217/78 , G06F2217/84
摘要： An apparatus for monitoring operation of a design under test (DUT) comprises a plurality of inputs comprising: an incoming clock edge input connected to detect active clock edges provided to a monitored clock gate; an outgoing clock edge input connected to detect active clock edges sent from the monitored clock gate; an enable input connected to detect enable signals provided to the monitored clock gate and any leaf clock gates connected to receive clock edges through the monitored clock gate; and a protocol input connected to receive protocol signals specifying when the monitored clock gate is required to output active clock edges. The apparatus also comprises a memory in communication with the inputs for storing values from the inputs, and a processor in communication with the memory and the inputs, the processor programmed to determine protocol compliance and to calculate energy consequences of dropping of active clock edges.

4. 发明授权

US09680523B1 System and method for transmitting ancillary data 有权
公开(公告)号：US09680523B1
公开(公告)日：2017-06-13
申请号：US15002780
申请日：2016-01-21
申请人： Microsemi Storage Solutions (U.S.), Inc.
发明人： Mathieu Gagnon , Paul Borsetti, Jr.
IPC分类号： H04B1/00 , H04B1/69 , H04B15/04
CPC分类号： H04B1/69 , H04B15/04
摘要： A method and system for encoding ancillary information at a transmitter in a high-speed communications network, the method comprising: generating an electromagnetic interference (EMI) reduction signal; receiving an ancillary data symbol; generating an EMI reduction signal variation based on the ancillary data symbol; and varying a characteristic of the EMI reduction signal based on the generated EMI reduction signal variation to encode the ancillary data symbol in the varied EMI reduction signal.

5. 发明授权

US09626309B1 Method and controller for requesting queue arbitration and coalescing memory access commands 有权
公开(公告)号：US09626309B1
公开(公告)日：2017-04-18
申请号：US14322556
申请日：2014-07-02
申请人： MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
发明人： Bradley Burke , Keith Graham Shaw
IPC分类号： G06F12/00 , G06F13/16 , G06F13/364
CPC分类号： G06F13/1642 , G06F13/364
摘要： Controller and method for requesting arbitration of a queue. The controller comprises a coalescing engine for determining a number of commands in a queue and requesting arbitration of the queue when a coalescing condition is satisfied. The method comprises determining the number of commands in a queue and requesting arbitration of the queue when a coalescing condition is satisfied.

6. 发明申请

US20170033741A1 ELECTRO-MECHANICAL VOLTAGE-CONTROLLED OSCILLATOR AND A METHOD FOR GENERATING TUNABLE BALANCED OSCILLATIONS 有权
标题翻译：电子机械电压控制振荡器和产生平衡平衡振荡的方法
公开(公告)号：US20170033741A1
公开(公告)日：2017-02-02
申请号：US15231250
申请日：2016-08-08
申请人： Microsemi Storage Solutions (U.S.), Inc.
发明人： Stanley HO , Hormoz Djahanshahi
IPC分类号： H03B5/36 , H03K4/50
CPC分类号： H03B5/368 , H03B5/364 , H03K4/50
摘要： A cross-coupled complementary balanced voltage-controlled oscillator and a method for operating same. The oscillator comprises an electro-mechanical resonator, and an oscillator core. The oscillator core comprises capacitvely cross-coupled complementary inverters and a resistor network. The oscillator may comprise a frequency tuning network having inductors for increasing the tuning range. The capacitance inhibit the inverters from latching to a static direct current state. The resistor network forms a high pass filter with the capacitance to inhibit relaxation oscillations. The method comprises enabling the resistor network to form a high pass filter and starting balanced oscillations in the oscillator, the capacitance of the high pass filter for inhibiting latching, and the high pass filter for inhibiting relaxation oscillations. The method may comprise tuning the frequency by varying the capacitance of the oscillator.
摘要翻译：交叉耦合互补平衡压控振荡器及其操作方法。振荡器包括机电谐振器和振荡器芯。振荡器芯包括电容交叉耦合互补逆变器和电阻网络。振荡器可以包括具有用于增加调谐范围的电感器的频率调谐网络。该电容可以抑制逆变器锁定到静态直流状态。电阻网络形成具有电容的高通滤波器以抑制弛豫振荡。该方法包括使电阻网络能够形成高通滤波器并启动振荡器中的平衡振荡，用于禁止锁存的高通滤波器的电容和用于抑制弛豫振荡的高通滤波器。该方法可以包括通过改变振荡器的电容来调谐频率。

7. 发明授权

US09432053B1 High speed LDPC decoder 有权
标题翻译：高速LDPC解码器
公开(公告)号：US09432053B1
公开(公告)日：2016-08-30
申请号：US14325172
申请日：2014-07-07
申请人： MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
发明人： Peter Graumann , Sean Gibb , Jonathan Eskritt
IPC分类号： H03M13/11
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1128 , H03M13/114 , H03M13/116
摘要： A method and decoder are provided to decode a Low Density Parity Check codeword. An additional check processor performs hard-decision processing functions on the LDPC codeword in order to avoid running unnecessary decoder iterations. The method comprises: receiving the ECC codeword at a memory, the received ECC codeword comprising ECC data bits, ECC parity bits, and error detection code bits; soft-decision decoding the received ECC codeword at a soft-decision decoder, to update the ECC codeword according to ECC parity check equations; hard-decision processing the received ECC codeword at a check processor, while the soft-decision decoder performs the soft-decision decoding, to verify the ECC data bits using the error detection code bits; terminating the soft-decision decoding when the ECC data bits are verified, regardless of whether the updated ECC codeword satisfies all of the ECC parity check equations; and, outputting the decoded ECC codeword from the memory after termination of the decoding.
摘要翻译：提供了一种方法和解码器来解码低密度奇偶校验码字。附加检查处理器在LDPC码字上执行硬判决处理功能，以避免运行不必要的解码器迭代。该方法包括：在存储器处接收ECC码字，所接收的ECC码字包括ECC数据比特，ECC奇偶校验位和错误检测码比特; 在软判决解码器处对接收的ECC码字进行软判决解码，以根据ECC奇偶校验方程更新ECC码字; 在软判决解码器执行软判决解码的同时，在检验处理器处理接收到的ECC码字，以使用错误检测码比特来验证ECC数据比特; 当ECC数据位被验证时终止软判决解码，而不管更新的ECC码字是否满足所有的ECC奇偶校验方程; 并且在解码结束之后从存储器输出解码的ECC码字。

8. 发明授权

US09344300B1 Apparatus and methods for variable peaking and low pass filtering equalization 有权
标题翻译：可变峰值和低通滤波均衡的装置和方法
公开(公告)号：US09344300B1
公开(公告)日：2016-05-17
申请号：US14296412
申请日：2014-06-04
申请人： MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
发明人： Predrag Acimovic , Vadim Milirud
IPC分类号： H04B3/04 , H04L25/03
CPC分类号： H04L25/03019 , H04B3/04 , H04L2025/037
摘要： This disclosure provides methods and apparatus for processing differential signals having non-inverted and inverted signals. An example apparatus has first and second circuit arms, each arm connected to receive one of the input signals. Each arm has a main signal path for carrying the respective input signal, and a secondary signal path for carrying a voltage divided and low-pass filtered version of the respective input signal. The outputs of the main and secondary signal paths are combined to produce equalized output signals.
摘要翻译：本公开提供了用于处理具有非反相和反相信号的差分信号的方法和装置。示例性装置具有第一和第二电路臂，每个臂连接以接收输入信号之一。每个臂具有用于承载相应输入信号的主信号路径和用于承载相应输入信号的分压和低通滤波版本的次信号路径。主信号路径和辅助信号路径的输出被组合以产生均衡的输出信号。

9. 发明申请

US20170244648A1 SYSTEMS AND METHODS FOR TRANSPORTATION OF MULTIPLE CONSTANT BITRATE DATA STREAMS 审中-公开
公开(公告)号：US20170244648A1
公开(公告)日：2017-08-24
申请号：US15438165
申请日：2017-02-21
申请人： Microsemi Storage Solutions (U.S.), Inc.
发明人： Richard Tsz Shiu TSE
IPC分类号： H04L12/927 , H04L12/841 , H04L29/08
CPC分类号： H04L47/801 , H04L47/10 , H04L47/28 , H04L47/36 , H04N21/2365 , H04N21/4347
摘要： Systems and methods are provided for transparently transmitting multiple constant bitrate (CBR) data streams over a packet network with reduced delay. Example embodiments provide packetizers and depacketizers for multiplexing and demultiplexing multiple common public radio interface (CPRI) data streams for transport between remote units and baseband units over packet networks. The systems and methods disclosed herein use time-division-multiplexing to map multiple CBR clients directly into a packet such that each CBR client can be recovered at the destination with its original clock and with information that allows its residence time in the packet domain to be calculated. The systems and methods disclosed herein allow packet based networks, such as the existing Packet Transport Network (PTN), to be used for C-RAN fronthaul applications with strict end-to-end delay requirements.

10. 发明申请

US20170177541A1 APPARATUS AND METHOD FOR TRANSFERRING DATA AND COMMANDS IN A MEMORY MANAGEMENT ENVIRONMENT 有权
公开(公告)号：US20170177541A1
公开(公告)日：2017-06-22
申请号：US15385158
申请日：2016-12-20
申请人： Microsemi Storage Solutions (U.S.), Inc.
发明人： Oren BERMAN , Stephen BATES
IPC分类号： G06F15/173 , H04L29/08 , G06F3/06
摘要： A method and system for transferring NVMe data over a network comprises using a discrete buffer memory device to generate a write command from an NVMe-over-RDMA write command request, store the user data from a client host of the network, and send an interrupt signal to a NVMe storage device of the network. The NVMe storage device retrieves the write command from the discrete buffer memory device and performs a direct memory access transfer of the stored user data from the discrete buffer memory device to the NVMe storage device. The discrete buffer memory device comprises a controller and a random access memory for generating commands and storing the commands in a submission queue of the random access memory. The controller can clear commands from the submission queue based on completion commands received in a completion queue of the random access memory.

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