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1. 发明授权

US06957371B2 Method and apparatus for embedded built-in self-test (BIST) of electronic circuits and systems 失效
标题翻译：电子电路和系统嵌入式自检（BIST）的方法和装置
公开(公告)号：US06957371B2
公开(公告)日：2005-10-18
申请号：US10142556
申请日：2002-05-10
申请人： Michael Ricchetti , Christopher J. Clark
发明人： Michael Ricchetti , Christopher J. Clark
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318544 , G01R31/318555
摘要： An embedded electronic system built-in self-test controller architecture that facilitates testing and debugging of electronic circuits and in-system configuration of programmable devices. The system BIST controller architecture includes an embedded system BIST controller, an embedded memory circuit, an embedded IEEE 1149.1 bus, and an external controller connector. The system BIST controller is coupled to the memory circuit and the IEEE 1149.1 bus, and coupleable to an external test controller via the external controller connector. The external test controller can communicate over the IEEE 1149.1 bus to program the memory and/or the system BIST controller circuitry, thereby enabling scan vectors to be debugged by the external test controller and then downloaded into the memory for subsequent application to a unit under test by the system BIST controller.
摘要翻译：嵌入式电子系统内置自检控制器架构，便于电子电路的测试和调试以及可编程器件的系统配置。系统BIST控制器架构包括嵌入式系统BIST控制器，嵌入式存储器电路，嵌入式IEEE 1149.1总线和外部控制器连接器。系统BIST控制器耦合到存储器电路和IEEE 1149.1总线，并通过外部控制器连接器与外部测试控制器耦合。外部测试控制器可以通过IEEE 1149.1总线进行通信，对存储器和/或系统BIST控制器电路进行编程，从而使扫描向量由外部测试控制器进行调试，然后下载到存储器中，以供后续应用到被测单元由系统BIST控制器。

2. 发明授权

US07406638B2 System and method for optimized test and configuration throughput of electronic circuits 失效
标题翻译：电子电路优化测试和配置吞吐量的系统和方法
公开(公告)号：US07406638B2
公开(公告)日：2008-07-29
申请号：US10896646
申请日：2004-07-22
申请人： Christopher J. Clark , Michael Ricchetti
发明人： Christopher J. Clark , Michael Ricchetti
IPC分类号： G01R31/28
CPC分类号： G01R31/31926 , G01R31/318533
摘要： A system and method for maximizing the throughput of test and configuration in the manufacture of electronic circuits and systems. The system employs a tester having a flexible parallel test architecture with expandable resources that can accommodate a selected number of units under test (UUTs). The parallel test architecture is configurable to accept separate banks or partitions of UUTs, thereby enabling the system to obtain an optimal or maximum achievable throughput of test and configuration for the UUTs. The system determines an optimal or maximum achievable throughput by calculating a desired number N of UUTs to be tested/configured in parallel. Testing or configuring this desired number of UUTs in parallel allows the handling time to be balanced with the test and configuration times, thereby resulting in the maximum achievable throughput.
摘要翻译：一种用于在电子电路和系统的制造中最大化测试和配置的吞吐量的系统和方法。该系统采用具有可扩展资源的灵活并行测试架构的测试仪，可扩展资源可容纳选定数量的被测单元（UUT）。并行测试体系结构可配置为接受UUT的独立库或分区，从而使系统能够获得UUT测试和配置的最佳或最大可实现吞吐量。系统通过计算要并联测试/配置的UUT的期望数量N来确定最佳或最大可实现吞吐量。并行测试或配置所需数量的UUT可以使处理时间与测试和配置时间相平衡，从而达到最大可实现的吞吐量。

3. 发明授权

US06988232B2 Method and apparatus for optimized parallel testing and access of electronic circuits 失效
标题翻译：用于电子电路优化并行测试和访问的方法和装置
公开(公告)号：US06988232B2
公开(公告)日：2006-01-17
申请号：US10119060
申请日：2002-04-09
申请人： Michael Ricchetti , Christopher J. Clark
发明人： Michael Ricchetti , Christopher J. Clark
IPC分类号： G06F11/00
CPC分类号： G01R31/318563 , G01R31/318516 , G01R31/318555 , G11C29/56 , G11C2029/2602
摘要： An architecture that provides stimulus data and verifies the response of multiple electronic circuits substantially in parallel for optimized testing, debugging, or programmable configuration of the circuits. The architecture includes a test bus, a primary test controller connected to the bus, and a plurality of local test controllers connected to the bus, in which each local test controller is coupleable to a respective circuit. The primary test controller sends stimulus data and expected response data over the bus to the respective local test controllers to perform parallel testing, debugging or programmable configuration of the circuits. Each local test controller applies the stimulus data and verifies the circuit response against the expected response data. Further, each local test controller stores the result of the verification for later retrieval by the primary test controller.
摘要翻译：提供激励数据并验证多个电子电路的响应基本上并行的架构，以优化电路的测试，调试或可编程配置。该架构包括测试总线，连接到总线的主测试控制器以及连接到总线的多个本地测试控制器，其中每个本地测试控制器可耦合到相应的电路。主测试控制器通过总线将激励数据和预期响应数据发送到相应的本地测试控制器，以执行电路的并行测试，调试或可编程配置。每个本地测试控制器应用刺激数据并根据预期响应数据验证电路响应。此外，每个本地测试控制器存储验证的结果以供主测试控制器稍后检索。

4. 发明申请

US20050210352A1 Method and apparatus for embedded Built-In Self-Test (BIST) of electronic circuits and systems 失效
标题翻译：电子电路和系统的嵌入式自检（BIST）的方法和装置
公开(公告)号：US20050210352A1
公开(公告)日：2005-09-22
申请号：US11130332
申请日：2005-05-16
申请人： Michael Ricchetti , Christopher Clark
发明人： Michael Ricchetti , Christopher Clark
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318544 , G01R31/318555
摘要： An embedded electronic system built-in self-test controller architecture that facilitates testing and debugging of electronic circuits and in-system configuration of programmable devices. The system BIST controller architecture includes an embedded system BIST controller, an embedded memory circuit, an embedded IEEE 1149.1 bus, and an external controller connector. The system BIST controller is coupled to the memory circuit and the IEEE 1149.1 bus, and coupleable to an external test controller via the external controller connector. The external test controller can communicate over the IEEE 1149.1 bus to program the memory and/or the system BIST controller circuitry, thereby enabling scan vectors to be debugged by the external test controller and then downloaded into the memory for subsequent application to a unit under test by the system BIST controller.
摘要翻译：嵌入式电子系统内置自检控制器架构，便于电子电路的测试和调试以及可编程器件的系统配置。系统BIST控制器架构包括嵌入式系统BIST控制器，嵌入式存储器电路，嵌入式IEEE 1149.1总线和外部控制器连接器。系统BIST控制器耦合到存储器电路和IEEE 1149.1总线，并通过外部控制器连接器与外部测试控制器耦合。外部测试控制器可以通过IEEE 1149.1总线进行通信，对存储器和/或系统BIST控制器电路进行编程，从而使扫描向量由外部测试控制器进行调试，然后下载到存储器中，以供后续应用到被测单元由系统BIST控制器。

5. 发明授权

US09152749B2 Management system, method and apparatus for licensed delivery and accounting of electronic circuits 有权
公开(公告)号：US09152749B2
公开(公告)日：2015-10-06
申请号：US10347904
申请日：2003-01-21
申请人： Michael Ricchetti , Christopher J. Clark
发明人： Michael Ricchetti , Christopher J. Clark
IPC分类号： G06F17/50 , G06F21/10 , G06Q30/00
CPC分类号： G06F17/5045 , G06F21/10 , G06F2217/66 , G06Q30/018
摘要： A system and method of licensing electronic circuit designs within target electronic circuits or devices that allows secure delivery and reliable accounting of the licensed circuit designs on a per-usage basis. The method includes determining whether an electronic circuit design is licensable for use within a target electronic circuit by verifying licensing information included in a set of predetermined vectors associated with the electronic circuit design. In the event it is determined that the electronic circuit design is licensable for use within the target electronic circuit, the set of vectors is applied to the target electronic circuit by a licensing controller. Next, in response to a predetermined event, an attribute of the licensing information is updated to indicate the licensed use of the electronic circuit design within the target circuit. The licensing system allows IP core providers and IP core users to account for the use of licensed electronic circuit designs on a per-usage basis with higher accuracy, thereby providing increased assurance that the electronic circuit designs are being licensed in a manner that is fair to all parties.

6. 发明申请

US20050060622A1 System and method for optimized test and configuration throughput of electronic circuits 失效
标题翻译：电子电路优化测试和配置吞吐量的系统和方法
公开(公告)号：US20050060622A1
公开(公告)日：2005-03-17
申请号：US10896646
申请日：2004-07-22
申请人： Christopher Clark , Michael Ricchetti
发明人： Christopher Clark , Michael Ricchetti
IPC分类号： G01R31/00 , G01R31/28 , G01R31/3185 , G01R31/319 , G06F17/00 , H05K20060101
CPC分类号： G01R31/31926 , G01R31/318533
摘要： A system and method for maximizing the throughput of test and configuration in the manufacture of electronic circuits and systems. The system employs a tester having a flexible parallel test architecture with expandable resources that can accommodate a selected number of units under test (UUTs). The parallel test architecture is configurable to accept separate banks or partitions of UUTs, thereby enabling the system to obtain an optimal or maximum achievable throughput of test and configuration for the UUTs. The system determines an optimal or maximum achievable throughput by calculating a desired number N of UUTs to be tested/configured in parallel. Testing or configuring this desired number of UUTs in parallel allows the handling time to be balanced with the test and configuration times, thereby resulting in the maximum achievable throughput.
摘要翻译：一种用于在电子电路和系统的制造中最大化测试和配置的吞吐量的系统和方法。该系统采用具有可扩展资源的灵活并行测试架构的测试仪，可扩展资源可容纳选定数量的被测单元（UUT）。并行测试体系结构可配置为接受UUT的独立库或分区，从而使系统能够获得UUT测试和配置的最佳或最大可实现吞吐量。系统通过计算要并联测试/配置的UUT的期望数量N来确定最佳或最大可实现吞吐量。并行测试或配置所需数量的UUT可以使处理时间与测试和配置时间相平衡，从而达到最大可实现的吞吐量。

7. 发明授权

US06594802B1 Method and apparatus for providing optimized access to circuits for debug, programming, and test 有权
标题翻译：用于为调试，编程和测试提供电路优化访问的方法和装置
公开(公告)号：US06594802B1
公开(公告)日：2003-07-15
申请号：US09716583
申请日：2000-11-20
申请人： Michael Ricchetti , Christopher J. Clark , Bulent I. Dervisoglu
发明人： Michael Ricchetti , Christopher J. Clark , Bulent I. Dervisoglu
IPC分类号： G06F1750
CPC分类号： G01R31/318555 , G01R31/31705
摘要： An access interface for accessing electrical nodes of an electronic circuit for programming, testing, and debugging the electronic circuit. The access interface includes a protocol generator and a data generator that may be programmed to apply control and/or data sequences directly to the electronic circuit. The access interface performs operational commands based upon a plurality of states included in a programmable state machine. By suitably programming the protocol generator, the data generator, and the state machine, electrical nodes of the electronic circuit can be accessed in reduced time using a reduced number of operations. The access interface is controlled by a test resource apparatus, which communicates with the electronic circuit connected to the access interface. The access interface may be implemented as a downloadable circuit, e.g., it may be programmed into a programmable logic device by the test resource apparatus. Alternatively, the access interface may be implemented as a fixed/permanent circuit in an ASIC.
摘要翻译：用于访问用于编程，测试和调试电子电路的电子电路的电节点的访问接口。访问接口包括协议生成器和可被编程为将控制和/或数据序列直接应用于电子电路的数据生成器。访问接口基于包括在可编程状态机中的多个状态来执行操作命令。通过适当地编程协议发生器，数据发生器和状态机，可以以减少的操作次数以减少的时间访问电子电路的电节点。访问接口由与连接到访问接口的电子电路进行通信的测试资源设备控制。访问接口可以被实现为可下载的电路，例如，其可以被测试资源设备编程到可编程逻辑设备中。或者，访问接口可以被实现为ASIC中的固定/永久电路。

8. 发明授权

US08443331B2 Synchronizing TAP controller after power is restored 失效
标题翻译：电源恢复后同步TAP控制器
公开(公告)号：US08443331B2
公开(公告)日：2013-05-14
申请号：US12853940
申请日：2010-08-10
申请人： Sophocles R. Metsis , Michael Ricchetti
发明人： Sophocles R. Metsis , Michael Ricchetti
IPC分类号： G06F17/50
CPC分类号： G01R31/318552
摘要： A system includes multiple TAP controllers that can be independently powered up and down. When a first TAP controller is powered up from a powered-down state while a second TAP controller is already in a powered-up state, the first TAP controller is reset causing the first TAP controller to enter a reset state in response to the power-up of a module on which the first TAP controller is disposed. The first TAP controller enters an idle state and its control signal is gated to hold the first TAP controller in the idle state until the second TAP controller enters the idle state. Subsequently, the first TAP controller is released such that the control signal supplied to the first and second TAP controllers are equal, thereby synchronizing the first TAP controller and the second TAP controller.
摘要翻译：一个系统包括多个TAP控制器，可以独立上电和下电。当第一TAP控制器从掉电状态通电而第二TAP控制器已经处于上电状态时，第一TAP控制器被复位，使得第一TAP控制器响应于电源接通而进入复位状态，在其上设置有第一TAP控制器的模块。第一TAP控制器进入空闲状态，并且其控制信号被选通以将第一TAP控制器保持在空闲状态，直到第二TAP控制器进入空闲状态。随后，释放第一TAP控制器，使得提供给第一和第二TAP控制器的控制信号相等，从而使第一TAP控制器和第二TAP控制器同步。

9. 发明申请

US20120042293A1 SYNCHRONIZING TAP CONTROLLER AFTER POWER IS RESTORED 失效
标题翻译：电源恢复后同步TAP控制器
公开(公告)号：US20120042293A1
公开(公告)日：2012-02-16
申请号：US12853940
申请日：2010-08-10
申请人： Sophocles R. Metsis , Michael Ricchetti
发明人： Sophocles R. Metsis , Michael Ricchetti
IPC分类号： G06F17/50
CPC分类号： G01R31/318552
摘要： A system includes multiple TAP controllers that can be independently powered up and down. When a first TAP controller is powered up from a powered-down state while a second TAP controller is already in a powered-up state, the first TAP controller is reset causing the first TAP controller to enter a reset state in response to the power-up of a module on which the first TAP controller is disposed. The first TAP controller enters an idle state and its control signal is gated to hold the first TAP controller in the idle state until the second TAP controller enters the idle state. Subsequently, the first TAP controller is released such that the control signal supplied to the first and second TAP controllers are equal, thereby synchronizing the first TAP controller and the second TAP controller.
摘要翻译：一个系统包括多个TAP控制器，可以独立上电和下电。当第一TAP控制器从掉电状态通电而第二TAP控制器已经处于上电状态时，第一TAP控制器被复位，使得第一TAP控制器响应于电源接通而进入复位状态，在其上设置有第一TAP控制器的模块。第一TAP控制器进入空闲状态，并且其控制信号被选通以将第一TAP控制器保持在空闲状态，直到第二TAP控制器进入空闲状态。随后，释放第一TAP控制器，使得提供给第一和第二TAP控制器的控制信号相等，从而使第一TAP控制器和第二TAP控制器同步。

10. 发明授权

US07574637B2 Method and apparatus for optimized parallel testing and access of electronic circuits 失效
标题翻译：用于电子电路优化并行测试和访问的方法和装置
公开(公告)号：US07574637B2
公开(公告)日：2009-08-11
申请号：US11286915
申请日：2005-11-23
申请人： Michael Ricchetti , Christopher J. Clark
发明人： Michael Ricchetti , Christopher J. Clark
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G01R31/318563 , G01R31/318516 , G01R31/318555 , G11C29/56 , G11C2029/2602
摘要： A Parallel Test Architecture (PTA) is provided that facilitates concurrent test, debug or programmable configuration of multiple electronic circuits (i.e., simultaneously). The PTA includes a communications path, a primary test controller, and a number of local test controllers. The primary controller provides stimulus, expected, and mask data to the local controllers over the communications path. The local controllers apply the stimulus data to the electronic circuits, receive resultant data generated by the circuits in response to the stimulus data, and locally verify the resultant data against the expected data substantially concurrently. When the communications path is implemented as an IEEE 1149.1 (JTAG) test bus, the primary controller can provide the expected and mask data to the local controllers over the TDO and TRSTN lines while the TAP controllers of the electronic circuits are in the Shift-IR or Shift-DR state to enable concurrent testing over a traditional five wire multi-drop IEEE 1149.1 test bus.
摘要翻译：提供了一种并行测试体系结构（PTA），它有助于同时测试，调试或可编程配置多个电子电路（即同时）。 PTA包括通信路径，主要测试控制器和多个本地测试控制器。主控制器通过通信路径向本地控制器提供刺激，预期和掩码数据。本地控制器将刺激数据应用于电子电路，响应于刺激数据接收由电路产生的结果数据，并且基本同时地基于预期数据对结果数据进行本地验证。当通信路径被实现为IEEE 1149.1（JTAG）测试总线时，主控制器可以通过TDO和TRSTN线路向本地控制器提供预期和掩蔽数据，而电子电路的TAP控制器处于Shift-IR 或Shift-DR状态，以实现传统的五线多点IEEE 1149.1测试总线的并发测试。

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