专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050017776A1 Chopped charge pump 有权
标题翻译：切断电荷泵
公开(公告)号：US20050017776A1
公开(公告)日：2005-01-27
申请号：US10874720
申请日：2004-06-23
申请人： Michael Keaveney , William Hunt
发明人： Michael Keaveney , William Hunt
IPC分类号： F04B20060101 , H02M20060101 , H03D13/00 , H03K3/017 , H03K3/0231 , H03L20060101 , H03L7/00 , H03L7/06 , H04B20060101
CPC分类号： H03K3/0231 , H03L7/0896
摘要： A chopped charge pump with matching up and down pulses including a first pair of current sources, a second pair of current sources, and a switching circuit for switching on in a first phase one of each pair to provide up current pulses and the other of each pair to provide down current pulses and switching on in a second phase the other of each pair to provide up current pulses and the one of each pair to provide down current pulses to offset error in the current response of the pairs of current sources.
摘要翻译：一种具有匹配的上升和下降脉冲的切断电荷泵，包括第一对电流源，第二对电流源和用于在每对中的第一相中接通以提供上升电流脉冲并且每个电流源中的另一个的开关电路以提供欠电流脉冲并且在第二相中接通每对中的另一相以提供电流脉冲，并且每对中的每一对以提供下降电流脉冲以抵消电流对的电流响应中的误差。

2. 发明授权

US08638139B2 Phase locked loop (PLL) based frequency sweep generator 有权
标题翻译：基于锁相环（PLL）的频率扫描发生器
公开(公告)号：US08638139B2
公开(公告)日：2014-01-28
申请号：US13229449
申请日：2011-09-09
申请人： Michael Keaveney , Patrick Walsh
发明人： Michael Keaveney , Patrick Walsh
IPC分类号： H03L7/06
CPC分类号： H03L7/197
摘要： A phase locked loop (PLL) based frequency sweep generator and methods for performing a frequency sweep are disclosed. In one implementation, the frequency sweep generator includes a circuit configured to generate a signal having a saw-tooth wave frequency ramp. The saw-tooth wave frequency ramp includes a rising portion and a resetting portion. The resetting portion has a shorter duration than the rising portion and includes a plurality of steps for decrementing the frequency of the signal.
摘要翻译：公开了一种基于锁相环（PLL）的频率扫描发生器和执行频率扫描的方法。在一个实现中，频率扫描发生器包括被配置为产生具有锯齿波频率斜坡的信号的电路。锯齿波频率斜坡包括上升部分和复位部分。复位部分具有比上升部分更短的持续时间，并且包括用于递减信号频率的多个步骤。

3. 发明授权

US07042970B1 Phase frequency detector with adjustable offset 有权
标题翻译：相位频率检测器，可调偏移量
公开(公告)号：US07042970B1
公开(公告)日：2006-05-09
申请号：US09882512
申请日：2001-06-15
申请人： Michael Keaveney , William Hunt , Michael Tuthill
发明人： Michael Keaveney , William Hunt , Michael Tuthill
IPC分类号： H03D3/24
CPC分类号： H03L7/0891 , H03D13/00 , H03L7/1976
摘要： A phase detection apparatus is described for use in a phase lock loop (PLL). The apparatus has a first input for a reference signal, a second input for a loop feedback signal and an output for the phase difference signal. Two D-type flips flops are provided, the first being clocked with the reference signal and the second with the loop feedback signal. The output of the second flip-flop is delayed relative to the first flip-flop, thereby effecting minimal overlap, when using the phase detection apparatus in a fractional- N phase lock loop, of the interpolator activity with that of the charge pump.
摘要翻译：描述了一种在锁相环（PLL）中使用的相位检测装置。该装置具有参考信号的第一输入端，环路反馈信号的第二输入端和相位差信号的输出端。提供两个D型翻转触发器，第一个用参考信号计时，第二个用循环反馈信号。第二触发器的输出相对于第一触发器延迟，从而当使用分数N锁相环中的相位检测装置时，使内插器活动与电荷泵的相互作用器活动相比最小化。

4. 发明申请

US20120062297A1 PHASE LOCKED LOOP (PLL) BASED FREQUENCY SWEEP GENERATOR 有权
标题翻译：基于相位锁相环（PLL）的频率振荡发生器
公开(公告)号：US20120062297A1
公开(公告)日：2012-03-15
申请号：US13229449
申请日：2011-09-09
申请人： Michael Keaveney , Patrick Walsh
发明人： Michael Keaveney , Patrick Walsh
IPC分类号： H03L7/089
CPC分类号： H03L7/197
摘要： A phase locked loop (PLL) based frequency sweep generator and methods for performing a frequency sweep are disclosed. In one implementation, the frequency sweep generator includes a circuit configured to generate a signal having a saw-tooth wave frequency ramp. The saw-tooth wave frequency ramp includes a rising portion and a resetting portion. The resetting portion has a shorter duration than the rising portion and includes a plurality of steps for decrementing the frequency of the signal.
摘要翻译：公开了一种基于锁相环（PLL）的频率扫描发生器和执行频率扫描的方法。在一个实现中，频率扫描发生器包括被配置为产生具有锯齿波频率斜坡的信号的电路。锯齿波频率斜坡包括上升部分和复位部分。复位部分具有比上升部分更短的持续时间，并且包括用于递减信号频率的多个步骤。

5. 发明申请

US20050231408A1 VARIABLE MODULUS INTERPOLATOR, AND A VARIABLE FREQUENCY SYNTHESISER INCORPORATING THE VARIABLE MODULUS INTERPOLATOR 有权
标题翻译：可变模块插值器和可变模块插值器的可变频率合成器
公开(公告)号：US20050231408A1
公开(公告)日：2005-10-20
申请号：US11149866
申请日：2005-06-10
申请人： Michael Keaveney , William Hunt
发明人： Michael Keaveney , William Hunt
IPC分类号： H03M3/02 , G06F17/17 , H03L7/183 , H03L7/197 , H03M7/00 , H03M7/36 , H03M3/00
CPC分类号： H03M7/3022 , G06F17/17 , H03L7/183 , H03L7/1976
摘要： An indirect variable frequency synthesiser for synthesising selectable frequencies from a reference frequency including a multi-divisor programmable frequency divider located in a feedback loop of the frequency synthesiser for dividing the feedback frequency in the feedback loop, the divider being responsive to a varying control signal applied thereto representative of a rational number of selectable value for selecting the divisor thereof for fractional division of the feedback frequency. A variable modulus interpolator converts a fractional part of the rational number of selectable value to a varying digital code representative of the fractional part of the rational number. The variable modulus interpolator includes an Nth order sigma-delta modulator having N sigma-delta stages cascaded in MASH configuration, where N is an integer greater than one, and is responsive to a selectable value of a numerator and a selectable value of a denominator of the fractional part of the rational number for outputting the varying digital code. A primary summer sums a digital code representative of a selectable value of the integer of the rational number with the varying digital code from the variable modulus interpolator to produce the varying control signal for applying to the programmable frequency divider.
摘要翻译：一种间接可变频率合成器，用于从包括位于频率合成器的反馈环路中的多因素可编程分频器的参考频率合成可选频率，用于分频反馈回路中的反馈频率，分频器响应于施加的变化的控制信号其代表用于选择其除数以用于反馈频率的分数除法的有选数量的可选值。可变模数插值器将有选数量的可选值的小数部分转换成代表有理数的小数部分的变化的数字代码。可变模数内插器包括具有在MASH配置中级联的N个Σ-Δ级的第N级Σ-Δ调制器，其中N是大于1的整数，并且响应于分子的可选择值和分母的可选择值用于输出变化的数字代码的有理数字的小数部分。初级夏令时，使用来自可变模数内插器的变化的数字代码来表示代表有理数整数的可选值的数字代码，以产生用于施加到可编程分频器的变化控制信号。

6. 发明申请

US20050024112A1 Pulse width modulated common mode feedback loop and method for differential charge pump 有权
标题翻译：脉宽调制共模反馈回路和差动电荷泵的方法
公开(公告)号：US20050024112A1
公开(公告)日：2005-02-03
申请号：US10873318
申请日：2004-06-22
申请人： Michael Keaveney
发明人： Michael Keaveney
IPC分类号： F04B20060101 , H02M20060101 , H03D13/00 , H03K3/017 , H03K3/0231 , H03L20060101 , H03L7/00 , H03L7/06 , H04B20060101
CPC分类号： H03K3/0231 , H03L7/0896
摘要： A pulse width modulated common mode feedback technique for a differential charge pump includes averaging the output of a differential charge pump to determine the common mode voltage; generating from the pump up and pump down pulses a set of up source pulses and down source pulses and a set of up sink pulses and down sink pulses and adjusting, in response to a difference between a reference voltage and the common mode voltage, the width of at least one of the sets of source and sink pulses to match the reference common mode voltages.
摘要翻译：用于差分电荷泵的脉宽调制共模反馈技术包括对差分电荷泵的输出进行平均以确定共模电压; 从泵浦产生泵浦脉冲一组上升源脉冲和下降脉冲以及一组上涌脉冲和下降脉冲，并且响应于参考电压和共模电压之间的差异来调整宽度的至少一组源极和峰值脉冲以匹配参考共模电压。

7. 发明申请

US20050024106A1 Charge pump system for fast locking phase lock loop 有权
公开(公告)号：US20050024106A1
公开(公告)日：2005-02-03
申请号：US10874641
申请日：2004-06-23
申请人： Michael Keaveney , Colin Lyden , Patrick Walsh
发明人： Michael Keaveney , Colin Lyden , Patrick Walsh
IPC分类号： F04B20060101 , H02M20060101 , H03D13/00 , H03K3/017 , H03K3/0231 , H03L20060101 , H03L7/00 , H03L7/06 , H04B20060101
CPC分类号： H03K3/0231 , H03L7/0896
摘要： A charge pump system for a fast locking phase lock loop includes a set n of charge pump units; and a control logic circuit for enabling the set of n charge pump units to produce up and down charge pulses with a nominal charge pump mismatch in a wide bandwidth mode; and in a narrow bandwidth mode enabling at least a subset of the n charge pump units sequentially to produce an average charge pump mismatch in narrow bandwidth mode that matches the nominal charge pump mismatch in the wide bandwidth mode.

8. 发明申请

US20070247233A1 Fractional-N synthesizer system and method 有权
标题翻译：分数N合成器系统和方法
公开(公告)号：US20070247233A1
公开(公告)日：2007-10-25
申请号：US11407646
申请日：2006-04-20
申请人： Michael Keaveney
发明人： Michael Keaveney
IPC分类号： H03L7/085
CPC分类号： H03L7/1976 , H03L7/07
摘要： A fractional-N synthesizer system including a plurality of fractional-N synthesizers all updated to simultaneously generate an output frequency from the same reference frequency, a phase locked loop having an output signal whose frequency is a fractional multiple of the input reference frequency; the phase locked loop including a frequency divider, an interpolator responsive to an input fraction to provide to the frequency divider an output which has a fractional value equal to on average, the input fraction; and a timeout circuit responsive to the reference frequency for generating an output a predetermined time after updating to initialize the interpolator in each synthesizer to the same start conditions for locking together the phase of the frequency outputs of all of the synthesizers at the updated frequency.
摘要翻译：一种分数N合成器系统，包括多个分数N个合成器，其全部被更新以同时从相同的参考频率产生输出频率;锁相环，具有其频率是输入参考频率的分数倍的输出信号; 所述锁相环包括分频器，所述内插器响应于输入分数，向所述分频器提供平均等于平均值的分数值的输出; 以及响应于参考频率的超时电路，用于在更新之后的预定时间产生输出，以将每个合成器中的内插器初始化为相同的起始条件，用于将所有合成器的频率输出的相位锁定在更新的频率上。

9. 发明申请

US20050057313A1 Differential charge pump phase lock loop (PLL) synthesizer with adjustable tuning voltage range 审中-公开
标题翻译：差分电荷泵锁相环（PLL）合成器，具有可调谐电压范围
公开(公告)号：US20050057313A1
公开(公告)日：2005-03-17
申请号：US10874603
申请日：2004-06-23
申请人： Michael Keaveney , Michael Tuthill
发明人： Michael Keaveney , Michael Tuthill
IPC分类号： F04B20060101 , H02M20060101 , H03D13/00 , H03K3/017 , H03K3/0231 , H03L20060101 , H03L7/00 , H03L7/06 , H04B20060101
CPC分类号： H03K3/0231 , H03L7/0896
摘要： A differential charge pump PLL synthesizer with adjustable tuning voltage range including a voltage controlled oscillator responsive to a tuning voltage to provide an output frequency. A phase detector circuit is responsive to a reference frequency and the sub-multiple of the output frequency for generating up and down pulses. A differential charge pump is responsive to the up and down pulses for generating positive and negative differential current pulses. A loop filter is responsive to the positive and negative differential current pulses for providing a differential voltage. A differential amplifier circuit is responsive to the differential voltage and a shift voltage applied at a voltage terminal for shifting the output voltage range of the differential amplifier circuit to provide a predetermined tuning voltage range.
摘要翻译：具有可调谐电压范围的差分电荷泵PLL合成器，包括响应调谐电压的压控振荡器以提供输出频率。相位检测器电路响应于参考频率和输出频率的子倍数以产生上升和下降脉冲。差分电荷泵响应于上升和下降脉冲以产生正和负的差分电流脉冲。环路滤波器响应正和负差分电流脉冲以提供差分电压。差分放大器电路响应于差分电压和施加在电压端子处的偏移电压，用于移位差分放大器电路的输出电压范围以提供预定的调谐电压范围。

10. 发明申请

US20050030072A1 Fast lock phase lock loop and method thereof 有权
公开(公告)号：US20050030072A1
公开(公告)日：2005-02-10
申请号：US10874646
申请日：2004-06-23
申请人： Michael Keaveney
发明人： Michael Keaveney
IPC分类号： F04B20060101 , H02M20060101 , H03D13/00 , H03K3/017 , H03K3/0231 , H03L20060101 , H03L7/00 , H03L7/06 , H04B20060101
CPC分类号： H03K3/0231 , H03L7/0896
摘要： A fast lock phase lock loop (PLL) with minimal phase disturbance when switching from wide bandwidth mode to narrow bandwidth mode including a phase frequency detector, a charge pump, a loop filter and a voltage controlled oscillator, and a sequencer circuit for, at a first time, initiating an increase in the charge pump current to increase the loop gain to widen the loop bandwidth and initiating a decrease in the resistance in the loop filter to increase the phase margin of the PLL in the wide bandwidth mode; at a second time, initiating a reduction in the charge pump current to reduce the loop gain and bandwidth, and; at a third time, initiating an increase in the resistance in the loop filter to increase the phase margin of the PLL in the narrow bandwidth mode.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式