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    • 1. 发明授权
    • Method and apparatus for adaptive hierarchical visibility in a tiled three-dimensional graphics architecture
    • 用于平铺三维图形架构中的自适应分层可见性的方法和装置
    • US06525726B1
    • 2003-02-25
    • US09432134
    • 1999-11-02
    • Feng XieMichael J. Shantz
    • Feng XieMichael J. Shantz
    • G06T1540
    • G06T15/40
    • A data processing system providing high performance three-dimensional graphics includes at least one system processor, chipset core logic, a graphics processor, and a Z-buffer. In one embodiment an adaptive hierarchical visibility (AHV) method performs occlusion-culling in a tiled 3D graphics hardware architecture. Polygon bins for each tile are bucket-sorted in order of increasing depth Z. Polygon bins are rendered starting with the bin closest to the viewer. After some number of bins are rendered, a single layer, hierarchical Z-buffer (HZ) may be constructed from the Z-buffer thus far accumulated for the rendered bins, if it would be cost effective to do so. Subsequent bins are rendered by first testing their polygons against the HZ buffer to see if they are hidden. Also described are an integrated circuit for implementing the AHV algorithm, and a computer-readable medium storing a data structure for implementing the AHV method and apparatus.
    • 提供高性能三维图形的数据处理系统包括至少一个系统处理器,芯片组核心逻辑,图形处理器和Z缓冲器。 在一个实施例中,自适应分层可见性(AHV)方法在平铺的3D图形硬件体系结构中执行遮挡剔除。 每个瓷砖的多边形料仓按照增加深度Z的顺序进行铲斗分类。多边形仓从最接近查看器的料仓开始。 在渲染一些数量的存储区之后,可以从Z缓冲区构建单层层次化Z缓冲区(HZ),以便如此才能实现这样做成本有效。 通过首先测试它们对HZ缓冲区的多边形来查看它们是否被隐藏,从而渲染后续的区块。 还描述了用于实现AHV算法的集成电路和存储用于实现AHV方法和装置的数据结构的计算机可读介质。
    • 5. 发明授权
    • Method and apparatus for multi-level demand caching of textures in a
graphics display device
    • 用于在图形显示装置中多层次需求缓存纹理的方法和装置
    • US6130680A
    • 2000-10-10
    • US982029
    • 1997-12-01
    • Michael Brian CoxMichael J. Shantz
    • Michael Brian CoxMichael J. Shantz
    • G06F12/08G06T1/60G06T11/40G06F13/00
    • G06F12/0875G06F12/0897G06T1/60
    • A computer graphics system for caching textures includes an L3 memory, an L2 cache, and an L1 cache for storing such textures and also includes a graphics accelerator (GA) for mapping these stored textures onto primitives for graphics display. The L3 memory, which has the largest capacity also has the slowest retrieval speed, while the L1 cache has the smallest capacity and the quickest retrieval speed. The textures are divided into a plurality of L2 texture blocks and each L2 texture block is subdivided into a plurality of L1 sub-blocks. During its rendering process, the GA searches the L1 cache for a particular L1 sub-block that is to be applied to a primitive. If such L1 sub-block is stored within the L1 cache, the GA will extract the desired texels (i.e., texture pixels) from the L1 sub-block and apply such texels to the primitive. If the L1 sub-block is not located in the L1 cache, the GA will search the L2 cache for the L1 sub-block. If it is found in the L2 cache, the GA will load the L1 sub-block to the L1 cache. However, if the L1 sub-block is not found within the L2 cache, the GA will load the L1 sub-block from the L3 memory to both the L1 and L2 caches. Advantageously, when the GA requires such L1 sub-block again, the GA will have a speedier access to the L1 sub-block via the L1 and L2 caches.
    • 用于缓存纹理的计算机图形系统包括L3存储器,L2高速缓存和用于存储这种纹理的L1高速缓存,并且还包括用于将这些存储的纹理映射到用于图形显示的基元上的图形加速器(GA)。 具有最大容量的L3存储器的检索速度最慢,而L1缓存具有最小的容量和最快的检索速度。 纹理分为多个L2纹理块,每个L2纹理块被细分为多个L1子块。 在其渲染过程中,GA在L1高速缓存中搜索要应用于原语的特定L1子块。 如果这样的L1子块被存储在L1高速缓存中,则GA将从L1子块中提取期望的纹理像素(即,纹理像素),并将这样的纹素应用于原始图像。 如果L1子块不位于L1高速缓存中,则GA将搜索L2高速缓存用于L1子块。 如果在L2高速缓存中找到,GA将把L1子块加载到L1高速缓存。 然而,如果在L2高速缓存中没有找到L1子块,则GA将L1 L3子块从L3存储器加载到L1和L2高速缓存。 有利地,当GA再次需要这样的L1子块时,GA将通过L1和L2高速缓存更快地访问L1子块。