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1. 发明申请

US20090231479A1 Image Sensor ADC and CDS per Column 有权
标题翻译：图像传感器ADC和CDS每列
公开(公告)号：US20090231479A1
公开(公告)日：2009-09-17
申请号：US12421948
申请日：2009-04-10
申请人： Jeffrey J. Zarnowski , Ketan V. Karia , Thomas Poonnen , Michael E. Joyner
发明人： Jeffrey J. Zarnowski , Ketan V. Karia , Thomas Poonnen , Michael E. Joyner
IPC分类号： H04N5/335
CPC分类号： H04N5/37455 , H03M1/1019 , H03M1/123 , H03M1/1235 , H03M1/56 , H04N5/335 , H04N5/35509 , H04N5/3575 , H04N5/361 , H04N5/365 , H04N5/378
摘要： A solid state imager converts analog pixel values to digital form on an arrayed per-column basis. A counter is coupled to an N-bit DAC to produce an analog ramp that varies corresponding to the contents of the counter. A ripple counter is associated with each respective column. A clock or a source of counts at a predetermined sequence supplies clock signals or counts to the counter elements. Column comparators gate the counter elements when the analog ramp equals the pixel value. The counter contents feed a video output bus to produce the digital video signal. Additional black-level readout counters elements can create and store a black level digital value that is subtracted from the pixel value to reduce fixed pattern noise. The counters may employ two's complement arithmetic. An additional array of buffer counter/latches can be employed. Ripple counters can be configured as counters to capture the digital video level, and then as shift registers to clock out the video levels to an output bus. The clock pulses or counts for the DAC counter and for the ripple counters can be at the same or different rates.
摘要翻译：固态成像器将阵列每列的模拟像素值转换为数字形式。计数器耦合到N位DAC以产生对应于计数器的内容而变化的模拟斜坡。纹波计数器与每个相应的列相关联。在预定序列上的时钟或计数源向计数器元件提供时钟信号或计数。当模拟斜坡等于像素值时，列比较器将计数器元件选通。计数器内容供给视频输出总线以产生数字视频信号。附加的黑电平读出计数器元件可以创建并存储从像素值中减去的黑电平数字值以减少固定模式噪声。计数器可以使用二进制补码算术。可以采用附加的缓冲计数器/锁存器阵列。纹波计数器可以配置为计数器来捕获数字视频电平，然后作为移位寄存器将视频电平时钟输出到输出总线。 DAC计数器和纹波计数器的时钟脉冲或计数可以是相同或不同的速率。

2. 发明授权

US07903159B2 Image sensor ADC and CDS per column 有权
标题翻译：图像传感器ADC和CDS每列
公开(公告)号：US07903159B2
公开(公告)日：2011-03-08
申请号：US12421948
申请日：2009-04-10
申请人： Jeffrey J. Zarnowski , Ketan V. Karia , Thomas Poonnen , Michael E. Joyner
发明人： Jeffrey J. Zarnowski , Ketan V. Karia , Thomas Poonnen , Michael E. Joyner
IPC分类号： H04N3/14 , H04N5/335
CPC分类号： H04N5/37455 , H03M1/1019 , H03M1/123 , H03M1/1235 , H03M1/56 , H04N5/335 , H04N5/35509 , H04N5/3575 , H04N5/361 , H04N5/365 , H04N5/378
摘要： A solid state imager converts analog pixel values to digital form on an arrayed per-column basis. A counter is coupled to an N-bit DAC to produce an analog ramp that varies corresponding to the contents of the counter. A ripple counter is associated with each respective column. A clock or a source of counts at a predetermined sequence supplies clock signals or counts to the counter elements. Column comparators gate the counter elements when the analog ramp equals the pixel value. The counter contents feed a video output bus to produce the digital video signal. Additional black-level readout counters elements can create and store a black level digital value that is subtracted from the pixel value to reduce fixed pattern noise. The counters may employ two's complement arithmetic. An additional array of buffer counter/latches can be employed. Ripple counters can be configured as counters to capture the digital video level, and then as shift registers to clock out the video levels to an output bus. The clock pulses or counts for the DAC counter and for the ripple counters can be at the same or different rates.
摘要翻译：固态成像器将阵列每列的模拟像素值转换为数字形式。计数器耦合到N位DAC以产生对应于计数器的内容而变化的模拟斜坡。纹波计数器与每个相应的列相关联。在预定序列上的时钟或计数源向计数器元件提供时钟信号或计数。当模拟斜坡等于像素值时，列比较器将计数器元件选通。计数器内容供给视频输出总线以产生数字视频信号。附加的黑电平读出计数器元件可以创建并存储从像素值中减去的黑电平数字值以减少固定模式噪声。计数器可以使用二进制补码算术。可以采用附加的缓冲计数器/锁存器阵列。纹波计数器可以配置为计数器来捕获数字视频电平，然后作为移位寄存器将视频电平时钟输出到输出总线。 DAC计数器和纹波计数器的时钟脉冲或计数可以是相同或不同的速率。

3. 发明授权

US07057150B2 Solid state imager with reduced number of transistors per pixel 失效
标题翻译：固态成像仪每像素数量减少
公开(公告)号：US07057150B2
公开(公告)日：2006-06-06
申请号：US10673591
申请日：2003-09-29
申请人： Jeffrey J. Zarnowski , Samuel D. Ambalavanar , Michael E. Joyner , Ketan V. Karia
发明人： Jeffrey J. Zarnowski , Samuel D. Ambalavanar , Michael E. Joyner , Ketan V. Karia
IPC分类号： H01J40/14
CPC分类号： H04N5/37457 , H01L27/14609 , H01L27/14641 , H04N5/335 , H04N5/347 , H04N5/363
摘要： A solid state imager with pixels arranged in columns and rows has the pixels are configured into groups of at least a first pixel and a second pixel, each said group sharing a pixel output transistor having a sense electrode and an output electrode and a reset transistor having a gate coupled to receive a reset signal and an output coupled to the sense electrode of the associated shared pixel output transistor. Each of the pixels has a photosensitive element whose output electrode is coupled to the sense electrode of the shared pixel output transistor and a gate electrode coupled to receive respective first and second pixel gating signals. This configuration reduces the number of FETs to two transistors for each pair of pixels, and also can achieve true correlated double sampling correction of FPN.
摘要翻译：具有排列成列和行的像素的固态成像器将像素配置成至少第一像素和第二像素的组，每个所述组共享具有感测电极和输出电极的像素输出晶体管，以及复位晶体管，其具有耦合以接收复位信号的栅极和耦合到相关联的共享像素输出晶体管的感测电极的输出。每个像素具有感光元件，其输出电极耦合到共享像素输出晶体管的感测电极，并且栅电极被耦合以接收相应的第一和第二像素门控信号。该配置将每对像素的FET数量减少到两个晶体管，并且还可以实现FPN的真实相关双采样校正。

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