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1. 发明授权

US4495564A Multi sub-channel adapter with single status/address register 失效
标题翻译：具有单个状态/地址寄存器的多子通道适配器
公开(公告)号：US4495564A
公开(公告)日：1985-01-22
申请号：US291741
申请日：1981-08-10
申请人： Wilburn D. Draper , Melvin T. Laakso
发明人： Wilburn D. Draper , Melvin T. Laakso
IPC分类号： G06F11/00 , G06F11/30 , G06F13/00 , G06F13/12 , G06F3/04
CPC分类号： G06F13/126
摘要： An improved adapter for a programmed control unit arranged to be operated in facilitating I/O operations between one or more I/O devices and a CPU through a channel. The improved adapter includes a local store which store has a hardware register dedicated to store device status and the associated address in connection with test I/O commands. Thus, in accordance with the method of the invention on receiving a status request the improved adapter responds immediately with a response indicating that the information is not immediately available, for example, a busy response. The improved adapter initiates an interrupt to the program control unit to obtain the requested status information, which is then stored in dedicated hardware registers of the local store. On the next subsequent test I/O command to the same address, the improved adapter responds with the status as read from the dedicated hardware register. In another aspect the invention provides an improved adapter which includes communication path means, for example hardware registers, passing data to and from the channel and attached devices, and a further hardware register of sufficient capacity to store a status word and an associated address. The adapter also includes a bus for transferring a status word and associated address from the attached control unit in response to a channel received command to the further hardware register and, control circuitry which is responsive to a subsequent status request and command associated with the associated address, for placing the status word from the further hardware register on the channel. The adapter supports both host or control unit initiated I/O status transfers, i.e. both synchronous and asynchronous.
摘要翻译：用于编程控制单元的改进的适配器被布置为通过通道来促进一个或多个I / O设备和CPU之间的I / O操作。改进的适配器包括本地存储器，其存储具有专用于存储设备状态的硬件寄存器和与测试I / O命令相关联的相关联的地址。因此，根据本发明的接收状态请求的方法，改进的适配器立即响应指示该信息不是立即可用的响应，例如忙响应。改进的适配器向程序控制单元启动中断以获得请求的状态信息，然后存储在本地存储器的专用硬件寄存器中。在接下来的测试I / O命令到同一地址时，改进的适配器将以从专用硬件寄存器读取的状态进行响应。在另一方面，本发明提供了一种改进的适配器，其包括通信路径装置，例如硬件寄存器，将数据传送到信道和连接的装置，以及具有足够容量以存储状态字和相关联的地址的另外的硬件寄存器。适配器还包括总线，用于响应于对另外的硬件寄存器的信道接收命令，从附加的控制单元传送状态字和相关联的地址;以及响应于随后的状态请求和与相关联的地址相关联的命令的控制电路用于将来自另外的硬件寄存器的状态字放在通道上。适配器支持主机或控制单元启动的I / O状态传输，即同步和异步。

2. 发明授权

US4159518A Auto-selection priority circuits for plural channel adapters 失效
标题翻译：多通道适配器的自动选择优先电路
公开(公告)号：US4159518A
公开(公告)日：1979-06-26
申请号：US812947
申请日：1977-07-05
申请人： Wilburn D. Draper , John D. Gentry , Michael T. Kawalec , Melvin T. Laakso
发明人： Wilburn D. Draper , John D. Gentry , Michael T. Kawalec , Melvin T. Laakso
IPC分类号： G06F13/26 , G06F13/374 , G06F3/04
CPC分类号： G06F13/26 , G06F13/374
摘要： In data processing systems of the type having a plurality of terminals connected by communication lines to a commmunications controller (CC) which assembles and manipulates the data from or to the terminals and one or more host central processing units (CPU's) to which the CC is connected by a number of channels, the CC will usually have a channel adapter unit (CA) for each channel and a processing unit to control the operations of the CC and to service the CA's in turn. It is necessary that the CA's be serviced with proper priorities to avoid unnecessary loss of information. An allocation of the proper priority is required where each CA can perform tasks of different urgency.The CC shown has four channel adapters communicating with four channels of the CPU's. All CA's can signal for an interrupt of the processor in the CC when CA service is needed. All CA's cause processor interrupts on the same interrupt level. A built-in priority allocation system will select for service that CA which wants to perform the task of highest priority among those CA's which are ready to perform a task. In the case of several requests of equal priority, a tie-breaking system comprises a loop circuit connecting all adapters and a signal sent in one direction around the loop from the last serviced adapter to select the next adapter which will be serviced.
摘要翻译：在具有通过通信线路连接到多个终端的通信通信控制器（CC）的多个终端的类型的数据处理系统中，所述通信控制器（CC）组合和操作来自终端的数据，以及CC的一个或多个主机中央处理单元（CPU）通过多个通道连接，CC通常将具有用于每个通道的通道适配器单元（CA）和用于控制CC的操作并依次服务CA的处理单元。有必要为适当的优先事项提供服务，以避免不必要的信息丢失。每个CA可以执行不同紧急性的任务时，需要分配适当的优先级。

3. 发明授权

US4224684A Receive/bypass circuit for subsystems in polling system 失效
标题翻译：轮询系统中子系统的接收/旁路电路
公开(公告)号：US4224684A
公开(公告)日：1980-09-23
申请号：US944960
申请日：1978-09-22
申请人： David E. Conner , Charles R. Hoffman , Melvin T. Laakso
发明人： David E. Conner , Charles R. Hoffman , Melvin T. Laakso
IPC分类号： G06F13/00 , G06F11/20 , H04L12/423 , H04L12/437 , H03K17/60 , H04Q1/20
CPC分类号： H04L12/423 , G06F11/20 , H04L12/437
摘要： A polling system includes a central processor and a plurality of subsystems connected in a loop to the central processor. A receive/bypass circuit in each subsystem includes a depletion mode field effect transistor having its drain and source electrodes connected in series in a bypass line at the subsystem. A control circuit is connected to a polling signal input line at each subsystem. When the subsystem has power, the control circuit routes the polling signal to a terminal device in the subsystem while establishing a conduction-inhibiting voltage at the gate electrode of the field effect transistor. When the subsystem is unpowered or out of service, a switching transistor in the control circuit isolates the terminal device from the polling signal input line. The polling signal bypasses an unpowered subsystem through the unbiased field effect transistor in the bypass line.
摘要翻译：轮询系统包括中央处理器和以循环连接到中央处理器的多个子系统。每个子系统中的接收/旁路电路包括耗尽型场效应晶体管，其漏极和源电极串联连接在子系统的旁路线路中。控制电路连接到每个子系统的轮询信号输入线。当子系统具有电源时，控制电路将轮询信号路由到子系统中的终端设备，同时在场效应晶体管的栅电极处建立导通抑制电压。当子系统无功或不工作时，控制电路中的开关晶体管将终端设备与轮询信号输入线隔离。轮询信号通过旁路线路中的无偏置场效应晶体管旁路无功子系统。

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