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1. 发明申请

US20090070612A1 MEMORY POWER MANAGEMENT 有权
标题翻译：存储电源管理
公开(公告)号：US20090070612A1
公开(公告)日：2009-03-12
申请号：US12199386
申请日：2008-08-27
申请人： Maxim Adelman , Jon C.R. Bennett
发明人： Maxim Adelman , Jon C.R. Bennett
IPC分类号： G06F1/08 , G06F12/08 , G06F12/06
CPC分类号： G11C11/4076 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/0608 , G06F3/064 , G06F3/0652 , G06F3/0688 , G06F3/0689 , G06F2212/7202 , G11C5/04 , G11C11/406 , G11C11/40611 , G11C11/4074 , G11C2211/4067 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory system is described, where a plurality of memory modules is connected to a memory controller. The power status of each of the memory modules is controlled, depending on the functions being performed by the memory module. When no read or write operation is being performed on a particular memory module, at least a portion of the circuitry may be operated in a lower power mode. A memory circuit associated with the memory module may be placed in a low power mode by disabling a clock. The memory circuit data integrity may be secured by issuing refresh commands while when the memory circuit is in the lower power mode, by enabling the clock, issuing the refresh command, and disabling the clock after completion of the refresh operation.
摘要翻译：描述了存储器系统，其中多个存储器模块连接到存储器控制器。根据存储器模块执行的功能，控制每个存储器模块的电源状态。当在特定存储器模块上不执行读取或写入操作时，电路的至少一部分可以在较低功率模式下操作。与存储器模块相关联的存储器电路可以通过禁止时钟而处于低功率模式。通过在存储器电路处于较低功率模式时通过发出刷新命令，通过使能时钟，发出刷新命令以及在完成刷新操作之后禁用时钟来保护存储器电路数据完整性。

2. 发明授权

US09384818B2 Memory power management 有权
标题翻译：内存电源管理
公开(公告)号：US09384818B2
公开(公告)日：2016-07-05
申请号：US12199386
申请日：2008-08-27
申请人： Maxim Adelman , Jon C. R. Bennett
发明人： Maxim Adelman , Jon C. R. Bennett
IPC分类号： G06F13/00 , G11C11/4076 , G06F1/32 , G11C5/04 , G11C11/406 , G11C11/4074 , G06F3/06
CPC分类号： G11C11/4076 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/0608 , G06F3/064 , G06F3/0652 , G06F3/0688 , G06F3/0689 , G06F2212/7202 , G11C5/04 , G11C11/406 , G11C11/40611 , G11C11/4074 , G11C2211/4067 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory system is described, where a plurality of memory modules is connected to a memory controller. The power status of each of the memory modules is controlled, depending on the functions being performed by the memory module. When no read or write operation is being performed on a particular memory module, at least a portion of the circuitry may be operated in a lower power mode. A memory circuit associated with the memory module may be placed in a low power mode by disabling a clock. The memory circuit data integrity may be secured by issuing refresh commands while when the memory circuit is in the lower power mode, by enabling the clock, issuing the refresh command, and disabling the clock after completion of the refresh operation.
摘要翻译：描述了存储器系统，其中多个存储器模块连接到存储器控制器。根据存储器模块执行的功能，控制每个存储器模块的电源状态。当在特定存储器模块上不执行读取或写入操作时，电路的至少一部分可以在较低功率模式下操作。与存储器模块相关联的存储器电路可以通过禁止时钟而处于低功率模式。通过在存储器电路处于较低功率模式时通过发出刷新命令，通过使能时钟，发出刷新命令以及在完成刷新操作之后禁用时钟来保护存储器电路数据完整性。

3. 发明申请

US20080109782A1 METHOD AND SYSTEM FOR PIN ASSIGNMENT 审中-公开
标题翻译：用于引脚分配的方法和系统
公开(公告)号：US20080109782A1
公开(公告)日：2008-05-08
申请号：US11550723
申请日：2006-10-18
申请人： Maxim Adelman , Stephen Fischer
发明人： Maxim Adelman , Stephen Fischer
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Methods and systems for assigning package pins of an electronic device to logical pins of a device design to be implemented on the electronic device are disclosed. An example method includes receiving a technology description file for the electronic device, where the technology description file includes a catalog of information for the electronic device. The method further includes receiving a design description file for the device design, where the design description file includes a catalog of information for the device design. A database is created from the technology description file and the design description file, where the database is for use in assigning the package pins of the electronic device to the logical pins of the device design. The method still further includes programmatically assigning the package pins of the electronic device to the logical pins of the device design using the database.
摘要翻译：公开了一种用于将电子设备的封装引脚分配给要在电子设备上实现的设备设计的逻辑引脚的方法和系统。示例性方法包括接收电子设备的技术描述文件，其中技术描述文件包括用于电子设备的信息目录。该方法还包括接收用于设备设计的设计描述文件，其中设计描述文件包括用于设备设计的信息目录。从技术描述文件和设计描述文件创建数据库，其中数据库用于将电子设备的封装引脚分配给器件设计的逻辑引脚。该方法还包括使用数据库以编程方式将电子设备的封装引脚分配给设备设计的逻辑引脚。

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