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1. 发明申请

US20050017849A1 Endpoint transmitter and power generation system 有权
标题翻译：端点发射机和发电系统
公开(公告)号：US20050017849A1
公开(公告)日：2005-01-27
申请号：US10627587
申请日：2003-07-24
申请人： Rolf Flen , Stuart Haug , Matthew Ruohoniemi
发明人： Rolf Flen , Stuart Haug , Matthew Ruohoniemi
IPC分类号： G06F20060101 , H04B3/54 , H04B3/56 , H04M11/04
CPC分类号： H04B3/542 , H04B2203/5433
摘要： An endpoint in a power distribution system includes a transmitter. The transmitter includes a transformer, a half-bridge driver, a first and second driver, and a resonant circuit. A primary winding from the transformer is coupled to a power distribution line, while the secondary winding is coupled to the transmitter. The half-bridge drive circuit selectively asserts drive signals. The resonant circuit has a natural resonant frequency in an audio frequency range. The half-bridge driver is arranged to selectively activate the first and second drivers such that the power-line is modulated with a square-wave signal at a frequency that is associated with encoded data. The half-bridge driver circuit can also be arranged to provide power to the transmitter, and to the endpoint.
摘要翻译：配电系统中的端点包括发射机。发射机包括变压器，半桥驱动器，第一和第二驱动器以及谐振电路。来自变压器的初级绕组耦合到配电线路，而次级绕组耦合到发射机。半桥驱动电路选择性地确定驱动信号。谐振电路在音频范围内具有固有的谐振频率。半桥驱动器被布置成选择性地激活第一和第二驱动器，使得以与编码数据相关联的频率的方波信号调制电力线。半桥驱动器电路也可以被布置成向发射器和端点提供电力。

2. 发明申请

US20070018850A1 Endpoint event processing system 有权
标题翻译：端点事件处理系统
公开(公告)号：US20070018850A1
公开(公告)日：2007-01-25
申请号：US11527008
申请日：2006-09-26
申请人： Rolf Flen , Stuart Haug , Matthew Ruohoniemi
发明人： Rolf Flen , Stuart Haug , Matthew Ruohoniemi
IPC分类号： G08C15/06
CPC分类号： H04B3/54 , G01D4/002 , H02J13/002 , H04B2203/5416 , H04B2203/542 , H04B2203/5466 , H04B2203/5483 , Y02B90/241 , Y04S20/32
摘要： An endpoint processor includes a processor block, a timer block, a memory block, and analog-to-digital converter. The timer block is arranged to provide a time based signal to the processor block. The memory block cooperates with the processor block. The analog-to-digital converter is arranged to provide an interface between an analog signal and the processor block. The analog signal includes encoded data from a power signal. The processor block is arranged to control a sampling rate that is associated with the analog-to-digital converter such that the analog signal is down-converted as an under-sampled signal. The processor block is arranged to extract the encoded data from the down-converted signal by executing a digital signal processing algorithm that is stored in the memory block. The digital signal processing algorithm is arranged to reject fundamental and harmonic frequencies that are associated with a power-line frequency that is associated with the power signal.
摘要翻译：端点处理器包括处理器块，定时器块，存储块和模数转换器。定时器块被布置成向处理器块提供基于时间的信号。存储块与处理器块协作。模数转换器被布置成提供模拟信号和处理器块之间的接口。模拟信号包括来自功率信号的编码数据。处理器块被布置成控制与模数转换器相关联的采样率，使得模拟信号被下变频为欠采样信号。处理器块被布置为通过执行存储在存储器块中的数字信号处理算法从下变频信号中提取编码数据。数字信号处理算法被布置为拒绝与与功率信号相关联的电力线频率相关联的基波和谐波频率。

3. 发明申请

US20050055586A1 Endpoint event processing system 有权
标题翻译：端点事件处理系统
公开(公告)号：US20050055586A1
公开(公告)日：2005-03-10
申请号：US10627590
申请日：2003-07-24
申请人： Rolf Flen , Stuart Haug , Matthew Ruohoniemi
发明人： Rolf Flen , Stuart Haug , Matthew Ruohoniemi
IPC分类号： G06F1/26
CPC分类号： H04B3/54 , G01D4/002 , H02J13/002 , H04B2203/5416 , H04B2203/542 , H04B2203/5466 , H04B2203/5483 , Y02B90/241 , Y04S20/32
摘要： An endpoint processor includes a processor block, a timer block, a memory block, and analog-to-digital converter. The timer block is arranged to provide a time based signal to the processor block. The memory block cooperates with the processor block. The analog-to-digital converter is arranged to provide an interface between an analog signal and the processor block. The analog signal includes encoded data from a power signal. The processor block is arranged to control a sampling rate that is associated with the analog-to-digital converter such that the analog signal is down-converted as an under-sampled signal. The processor block is arranged to extract the encoded data from the down-converted signal by executing a digital signal processing algorithm that is stored in the memory block. The digital signal processing algorithm is arranged to reject fundamental and harmonic frequencies that are associated with a power-line frequency that is associated with the power signal.
摘要翻译：端点处理器包括处理器块，定时器块，存储块和模数转换器。定时器块被布置成向处理器块提供基于时间的信号。存储块与处理器块协作。模数转换器被布置成提供模拟信号和处理器块之间的接口。模拟信号包括来自功率信号的编码数据。处理器块被布置成控制与模数转换器相关联的采样率，使得模拟信号被下变频为欠采样信号。处理器块被布置为通过执行存储在存储器块中的数字信号处理算法从下变频信号中提取编码数据。数字信号处理算法被布置为拒绝与与功率信号相关联的电力线频率相关联的基波和谐波频率。

4. 发明申请

US20050017848A1 Endpoint receiver system 有权
标题翻译：端点接收机系统
公开(公告)号：US20050017848A1
公开(公告)日：2005-01-27
申请号：US10627397
申请日：2003-07-24
申请人： Rolf Flen , Stuart Haug , Matthew Ruohoniemi
发明人： Rolf Flen , Stuart Haug , Matthew Ruohoniemi
IPC分类号： H04B3/54 , H04M11/04
CPC分类号： H04B3/542 , H04B2203/5433
摘要： An endpoint is configured for communication with a distribution substation. The endpoint includes a receiver conditioning block and a receiver processing block. The receiver conditioning block is positioned downstream from the distribution substation, and arranged to provide an analog signal that is responsive to the power signal from the distribution line. The receiver processing block is configured to extract encoded data from the power signal by under-sampling the analog signal, and processing the under-sampled analog signal such that fundamental and harmonic frequencies associated with the power signal are suppressed. Command signals from the distribution substation are extracted from the power-line. Each endpoint is addressable by an ID code, and is configurable via downstream command signals that are associated with the ID code. The endpoint collects data at demand based and schedule based intervals.
摘要翻译：端点配置为与分配变电站进行通信。端点包括接收器调节块和接收器处理块。接收器调节块位于分配变电站的下游，并且被布置成提供响应于来自分配线的功率信号的模拟信号。接收器处理块被配置为通过对模拟信号进行欠采样来处理来自功率信号的编码数据，并且处理欠采样的模拟信号，从而抑制与功率信号相关联的基频和谐波频率。从电力线提取配电站的指令信号。每个端点可以通过ID代码寻址，并且可以通过与ID代码相关联的下游命令信号进行配置。端点根据需求和基于时间表的时间间隔收集数据。

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