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1. 发明授权

US07834420B2 Semiconductor integrated circuit device and process for manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07834420B2
公开(公告)日：2010-11-16
申请号：US12335302
申请日：2008-12-15
申请人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
发明人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
IPC分类号： H01L29/00 , H01L21/8234
CPC分类号： H01L27/11 , G11C11/412 , G11C11/4125 , H01L21/76895 , H01L27/0203 , H01L27/0207 , H01L27/1104 , Y10S257/904
摘要： A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
摘要翻译：一种完整的CMOS型SRAM，其存储单元由六个MISFET组成，其中一对用于连接CMOS反相器的输入/输出端的局部布线由难熔金属硅化物层形成，该难熔金属硅化物层形成在构成个体的第一导电层上存储单元的驱动MISFET，转移MISFET和负载MISFET的栅极电极，其中形成在局部布线上的参考电压线被布置成叠加在局部布线上以形成电容元件。此外，通过在第一导电层上叠加局部布线，在局部布线和第一导电层之间形成电容元件。此外，通过使用诸如硅化的电阻降低装置来形成局部布线。此外，公开了用于降低转移MISFET的栅电极的电阻和用于形成局部布线的装置的手段。

2. 发明申请

US20080099854A1 Semiconductor integrated circuit device and process for manufacturing the same 失效
公开(公告)号：US20080099854A1
公开(公告)日：2008-05-01
申请号：US11834095
申请日：2007-08-06
申请人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
发明人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , G11C11/412 , G11C11/4125 , H01L21/76895 , H01L27/0203 , H01L27/0207 , H01L27/1104 , Y10S257/904
摘要： A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

3. 发明申请

US20080073726A1 Semiconductor integrated circuit device and process for manufacturing the same 失效
公开(公告)号：US20080073726A1
公开(公告)日：2008-03-27
申请号：US11826491
申请日：2007-07-16
申请人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
发明人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
IPC分类号： H01L27/088
CPC分类号： H01L27/11 , G11C11/412 , G11C11/4125 , H01L21/76895 , H01L27/0203 , H01L27/0207 , H01L27/1104 , Y10S257/904
摘要： A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

4. 发明授权

US5754467A Semiconductor integrated circuit device and process for manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5754467A
公开(公告)日：1998-05-19
申请号：US451117
申请日：1995-05-25
申请人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
发明人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
IPC分类号： G11C11/412 , H01L21/768 , H01L21/8244 , H01L27/11 , G11C11/00 , H01L25/00 , H01L29/76
CPC分类号： H01L27/11 , G11C11/4125 , H01L21/76895 , H01L27/0203 , H01L27/0207 , H01L27/1104 , G11C11/412 , Y10S257/904
摘要： A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacitor. The capacitor is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using a structure with decreased resistance such as silicided structure. In addition, there are made common the processing for lowering the resistance of the gate electrode of the transfer MISFETs and the processing for forming the local wiring lines.
摘要翻译：一种完整的CMOS型SRAM，其存储单元由六个MISFET组成，其中一对用于连接CMOS反相器的输入/输出端的局部布线由难熔金属硅化物层形成，该难熔金属硅化物层形成在构成个体的第一导电层上存储单元的驱动MISFET，转移MISFET和负载MISFET的栅极电极，其中形成在局部布线上的参考电压线被布置成叠加在局部布线上以形成电容器。电容器通过将局部布线叠置在第一导电层上而形成在局部布线和第一导电层之间。此外，通过使用诸如硅化结构的电阻降低的结构形成局部布线。此外，公开了用于降低转移MISFET的栅电极的电阻和用于形成局部布线的处理的处理。

5. 发明授权

US5607866A Method of fabricating a semiconductor device having silicide layers for electrodes 失效
标题翻译：制造具有用于电极的硅化物层的半导体器件的方法
公开(公告)号：US5607866A
公开(公告)日：1997-03-04
申请号：US458112
申请日：1995-06-02
申请人： Kazushige Sato , Atsuo Watanabe , Kenichi Kikushima , Nobuo Owada , Masaya Iida
发明人： Kazushige Sato , Atsuo Watanabe , Kenichi Kikushima , Nobuo Owada , Masaya Iida
IPC分类号： H01L21/285 , H01L21/8249 , H01L27/06 , H01L21/265
CPC分类号： H01L21/8249 , H01L21/28518 , H01L27/0635 , Y10S148/009
摘要： In a method of fabricating a semiconductor device having a MISFET and/or bipolar transistor and/or a resistor formed with different surface portions of a single silicon semiconductor substrate in which a silicide layer is formed on each of source/drain regions of the MISFET and/or collector contact region and extrinsic base region of the bipolar transistor and/or contact regions of the resistor, the bipolar transistor has its emitter region formed by diffusing an impurity contained in doped polysilicon film serving as an emitter electrode of the bipolar transistor into a part of its base region. The resistor may have a resistive region formed in a surface portion of the substrate and may be covered with an insulating film and a doped polysilicon film thereon or may have a doped polysilicon film formed over a surface portion of the substrate as a resistor element. These doped polysilicon films in the resistor are films which are formed in the same step as that for the doped silicon film serving as the emitter electrode in the bipolar transistor. Each of the doped polysilicon film in the bipolar transistor and that in the resistor are covered with an insulating film before a refractory metal film is formed over a whole surface of the substrate to prevent formation of silicide films on the doped polysilicon films in the bipolar transistor and resistor.
摘要翻译：在制造具有MISFET和/或双极晶体管和/或形成有单晶硅半导体衬底的不同表面部分的电阻器的半导体器件的方法中，其中在MISFET的每个源极/漏极区域上形成硅化物层， /或集电极接触区域和双极性晶体管的非本征基极区域和/或电阻器的接触区域，双极晶体管的发射极区域通过将掺杂多晶硅膜中所含的杂质扩散到双极型晶体管的发射电极而形成，其基地区的一部分。电阻器可以具有形成在衬底的表面部分中的电阻区域，并且可以在其上覆盖绝缘膜和掺杂多晶硅膜，或者可以在衬底的表面部分上形成作为电阻器元件的掺杂多晶硅膜。电阻器中的这些掺杂多晶硅膜是与双极晶体管中的发射极电极的掺杂硅膜相同的步骤形成的膜。在双极晶体管的整个表面上形成耐火金属膜之前，双极晶体管中的每个掺杂多晶硅膜和电阻器中的掺杂多晶硅膜都被绝缘膜覆盖，以防止在双极晶体管中的掺杂多晶硅膜上形成硅化物膜和电阻。

6. 发明授权

US08133780B2 Semiconductor integrated circuit device and process for manufacturing the same 失效
公开(公告)号：US08133780B2
公开(公告)日：2012-03-13
申请号：US13044652
申请日：2011-03-10
申请人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
发明人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
IPC分类号： H01L21/8234 , H01L29/00
CPC分类号： H01L27/11 , G11C11/412 , G11C11/4125 , H01L21/76895 , H01L27/0203 , H01L27/0207 , H01L27/1104 , Y10S257/904
摘要： A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

7. 发明申请

US20100164015A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20100164015A1
公开(公告)日：2010-07-01
申请号：US12644461
申请日：2009-12-22
申请人： Kenji MIYAKOSHI , Shinichiro WADA , Junji NOGUCHI , Koichiro MIYAMOTO , Masaya IIDA , Masafumi SUEFUJI
发明人： Kenji MIYAKOSHI , Shinichiro WADA , Junji NOGUCHI , Koichiro MIYAMOTO , Masaya IIDA , Masafumi SUEFUJI
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823412
摘要： When MOS transistors having a plurality of threshold voltages in which a source and a drain form a symmetrical structure are mounted on the same substrate, electrically-symmetrical characteristics is provided with respect to an exchange of the source and the drain in each MOS transistor. A MOS transistor having a large threshold voltage is provided with a halo diffusion region, and halo implantation is not performed on a MOS transistor having a small threshold voltage.
摘要翻译：当源极和漏极形成对称结构的多个阈值电压的MOS晶体管被安装在同一衬底上时，相对于每个MOS晶体管中的源极和漏极的交换来提供电对称特性。具有大阈值电压的MOS晶体管具有卤素扩散区域，并且不对具有小阈值电压的MOS晶体管进行晕圈注入。

8. 发明申请

US20090140349A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20090140349A1
公开(公告)日：2009-06-04
申请号：US12335302
申请日：2008-12-15
申请人： Shuji IKEDA , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
发明人： Shuji IKEDA , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
IPC分类号： H01L27/092
CPC分类号： H01L27/11 , G11C11/412 , G11C11/4125 , H01L21/76895 , H01L27/0203 , H01L27/0207 , H01L27/1104 , Y10S257/904
摘要： A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
摘要翻译：一种完整的CMOS型SRAM，其存储单元由六个MISFET组成，其中一对用于连接CMOS反相器的输入/输出端的局部布线由难熔金属硅化物层形成，该难熔金属硅化物层形成在构成个体的第一导电层上存储单元的驱动MISFET，转移MISFET和负载MISFET的栅极电极，其中形成在局部布线上的参考电压线被布置成叠加在局部布线上以形成电容元件。此外，通过在第一导电层上叠加局部布线，在局部布线和第一导电层之间形成电容元件。此外，通过使用诸如硅化的电阻降低装置来形成局部布线。此外，公开了用于降低转移MISFET的栅电极的电阻和用于形成局部布线的装置的手段。

9. 发明授权

US07511377B2 Semiconductor integrated circuit device and process for manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07511377B2
公开(公告)日：2009-03-31
申请号：US11834095
申请日：2007-08-06
申请人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
发明人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
IPC分类号： H01L23/52 , H01L29/00
CPC分类号： H01L27/11 , G11C11/412 , G11C11/4125 , H01L21/76895 , H01L27/0203 , H01L27/0207 , H01L27/1104 , Y10S257/904
摘要： A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
摘要翻译：一种完整的CMOS型SRAM，其存储单元由六个MISFET组成，其中一对用于连接CMOS反相器的输入/输出端的局部布线由难熔金属硅化物层形成，该难熔金属硅化物层形成在构成个体的第一导电层上存储单元的驱动MISFET，转移MISFET和负载MISFET的栅极电极，其中形成在局部布线上的参考电压线被布置成叠加在局部布线上以形成电容元件。此外，通过在第一导电层上叠加局部布线，在局部布线和第一导电层之间形成电容元件。此外，通过使用诸如硅化的电阻降低装置来形成局部布线。此外，公开了用于降低转移MISFET的栅电极的电阻和用于形成局部布线的装置的手段。

10. 发明申请

US20070241382A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20070241382A1
公开(公告)日：2007-10-18
申请号：US11765265
申请日：2007-06-19
申请人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
发明人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
IPC分类号： H01L27/108
CPC分类号： H01L27/11 , G11C11/412 , G11C11/4125 , H01L21/76895 , H01L27/0203 , H01L27/0207 , H01L27/1104 , Y10S257/904
摘要： A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
摘要翻译：一种完整的CMOS型SRAM，其存储单元由六个MISFET组成，其中一对用于连接CMOS反相器的输入/输出端的局部布线由难熔金属硅化物层形成，该难熔金属硅化物层形成在构成个体的第一导电层上存储单元的驱动MISFET，转移MISFET和负载MISFET的栅极电极，其中形成在局部布线上的参考电压线被布置成叠加在局部布线上以形成电容元件。此外，通过在第一导电层上叠加局部布线，在局部布线和第一导电层之间形成电容元件。此外，通过使用诸如硅化的电阻降低装置来形成局部布线。此外，公开了用于降低转移MISFET的栅电极的电阻和用于形成局部布线的装置的手段。

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