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1. 发明授权

US5272665A Semiconductor memory with improved sense amplifier layout 失效
标题翻译：具有改善的读出放大器布局的半导体存
公开(公告)号：US5272665A
公开(公告)日：1993-12-21
申请号：US903258
申请日：1992-06-24
申请人： Masaru Uesugi
发明人： Masaru Uesugi
IPC分类号： G11C7/18 , G11C13/00
CPC分类号： G11C7/18
摘要： A semiconductor memory has a matrix of memory cells crossed by word lines and bit lines. In each group of eight adjacent bit lines, a first sense amplifier is coupled to the first and sixth bit lines, a second sense amplifier to the third and eighth bit lines, a third sense amplifier to the second and fifth bit lines, and a fourth sense amplifier to the fourth and seventh bit lines. The first and third sense amplifiers are located side by side on one side of the memory matrix, between the second and fifth bit lines. The second and fourth sense amplifiers are located side by side on the opposite side of the memory matrix, between the fourth and seventh bit lines.
摘要翻译：半导体存储器具有由字线和位线交叉的存储器单元的矩阵。在八个相邻位线的每组中，第一读出放大器耦合到第一和第六位线，到第三和第八位线的第二读出放大器，到第二和第五位线的第三读出放大器，以及第四位线读出放大器到第四和第七位线。第一和第三感测放大器位于存储器矩阵的一侧上，位于第二和第五位线之间。第二和第四读出放大器并排地位于存储器矩阵的相对侧，位于第四和第七位线之间。

2. 发明授权

US5103158A Reference voltage generating circuit 失效
标题翻译：参考电压发生电路
公开(公告)号：US5103158A
公开(公告)日：1992-04-07
申请号：US682189
申请日：1991-04-08
申请人： Shizuo Cho , Tsuneo Takano , Masaru Uesugi
发明人： Shizuo Cho , Tsuneo Takano , Masaru Uesugi
IPC分类号： H01L27/04 , G05F1/46 , G05F3/24 , G11C11/407 , H01L21/822
CPC分类号： G05F1/462 , G05F3/245
摘要： A reference voltage generating circuit in a CMOS semiconductor integrated circuit comprises a first reference voltage circuit for generating a first reference voltage by means of a MOS transistor having a first channel type, a second reference voltage circuit for generating a second reference voltage by means of a MOS transistor having a second channel type, and a comparator circuit for comparing the first and second reference voltages and feeding back the output corresponding to the result of the comparison, to the first reference voltage circuit to produce a third reference voltage.

3. 发明授权

US5001669A Semiconductor memory circuit having dummy cells connected to twisted bit lines 失效
标题翻译：半导体存储器电路具有连接到扭曲位线的虚设单元
公开(公告)号：US5001669A
公开(公告)日：1991-03-19
申请号：US385727
申请日：1989-07-26
申请人： Shizuo Cho , Masaru Uesugi
发明人： Shizuo Cho , Masaru Uesugi
IPC分类号： G11C11/401 , G11C7/14 , G11C7/18 , G11C11/4099
CPC分类号： G11C7/14 , G11C11/4099 , G11C7/18
摘要： A semiconductor memory circuit includes a plurality of bit line pairs each having intersecting portions where the paired bit lines intersect each other, and a plurality of pairs of memory word lines intersecting the bit lines in a direction substantially perpendicular to the bit lines. A plurality of memory cells are individually connected to the memory word lines and bit lines at intersections of one of the memory word lines of the individual memory word line pairs and one of the bit lines of the individual bit line pairs and at intersections of the other of the paired memory word lines and the other of the paired bit lines for storing charges each being associated with data to be sorted. A pair of dummy word lines are interposed between the intersecting portions of the bit lines and intersect the bit line pairs in a direction substantially perpendicular to the bit line pairs. A plurality of dummy cells are individually connected between the dummy word line pairs and the bit line pairs at intersections of one of the dummy word lines of the individual word line pairs and one of the bit lines of the individual bit line pairs and at intersections of the other of the paired dummy word lines and the other of the paired bit lines.
摘要翻译：半导体存储器电路包括多个位线对，每个位线对具有成对的位线相交的相交部分，以及与位线基本上垂直于位线的方向相交的多对存储器字线。多个存储器单元分别连接到各个存储字线对的一个存储字线和各位线对中的一个位线和另一个的交叉点之间的交叉处的存储器字线和位线的配对存储器字线和用于存储每个与要排序的数据相关联的电荷的成对位线中的另一个。一对虚拟字线插入在位线的相交部分之间，并且在与位线对基本垂直的方向上与位线对相交。多个虚拟单元分别连接在虚拟字线对和位线对之间，在各个字线对之间的一个虚拟字线和各个位线对的位线之一的交点处和配对的虚拟字线中的另一个和配对的位线中的另一个。

4. 发明授权

US5058073A CMOS RAM having a complementary channel sense amplifier 失效
标题翻译： CMOS RAM具有互补通道读出放大器
公开(公告)号：US5058073A
公开(公告)日：1991-10-15
申请号：US608035
申请日：1990-10-30
申请人： Shizuo Cho , Masaru Uesugi
发明人： Shizuo Cho , Masaru Uesugi
IPC分类号： G11C11/4091
CPC分类号： G11C11/4091
摘要： A semiconductor memory such as a dynamic RAM (Random Access Memory) implemented by complementary MOS (CMOS) transistors includes a plurality of bit line pairs each constituted by a first and a second complementary bit line for transferring data, and a plurality of word lines extending across the bit line pairs. A plurality of memory cells are located at the intersecting points of the bit line pairs and word lines and connected to the latter for storing data therein. A plurality of sense amplifier circuits are each associated with respect to one of the bit line pairs for sensing potentials on a first and a second node associated with the bit line pair and amplifying the sensed potentials. Each of the sense amplifier circuits includes a first and a second sense amplifier of opposite polarity. A plurality of first field effect transistors (FETs) each has a source-drain path for connecting to the first node the first bit line of respective one of the bit line pairs. A plurality of second FETs each has a source-drain path for connecting to the second node the second bit line of respective one of the bit line pairs. The plurality of first and second field effect transistors individually have commonly connected control electrodes to which a gate signal is applied. The plurality of first and second field effect transistors are complementarily controlled in response to the gate signal to transfer one of the potentials on the first and second bit lines to one of the first and second sense amplifiers.
摘要翻译：由互补MOS（CMOS）晶体管实现的诸如动态RAM（随机存取存储器）的半导体存储器包括多个位线对，每个位线对由用于传送数据的第一和第二互补位线构成，并且多个字线延伸跨位线对。多个存储器单元位于位线对和字线的交叉点处，并与之连接，用于在其中存储数据。多个读出放大器电路各自相对于一个位线对相关联，用于感测与位线对相关联的第一和第二节点上的电位并放大感测的电位。每个读出放大器电路包括具有相反极性的第一和第二读出放大器。多个第一场效应晶体管（FET）各自具有用于将相应一个位线对的第一位线连接到第一节点的源极 - 漏极路径。多个第二FET各自具有用于将相应一个位线对的第二位线连接到第二节点的源极 - 漏极路径。多个第一和第二场效应晶体管分别具有施加栅极信号的共同连接的控制电极。多个第一和第二场效应晶体管响应于栅极信号被互补地控制，以将第一和第二位线上的电位之一传递到第一和第二读出放大器之一。

5. 发明授权

US4763304A Semiconductor random access memory device having switchable input and output bit forms 失效
标题翻译：半导体随机存取存储器件具有可切换的输入和输出位形式
公开(公告)号：US4763304A
公开(公告)日：1988-08-09
申请号：US882534
申请日：1986-07-07
申请人： Masaru Uesugi
发明人： Masaru Uesugi
IPC分类号： G11C7/00 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/41 , G11C29/00 , G11C29/34
CPC分类号： G11C7/1006
摘要： A semiconductor random access memory device having input terminals for receiving multi-bit data and output terminals for transmitting multi-bit data includes a memory cell matrix connected to a number of pairs of data lines and including a number of memory cells. Also included is an address decoder circuit which is responsive to an external address signal for providing address selection signals and a number of data input control circuits for receiving both 1-bit data signal and 1-bit signals of the multi-bit data and for providing as a pair of complementary signals either the 1-bit data signal or the one bit signal of the multi-bit data signal in response to various signals input thereto. A number of data input/output switching circuits and bit data output control circuits and 1-bit data output circuits and bit signal output control circuits are also provided for properly outputting either the 1-bit data or one bit signal of the multi-bit data from the output of the semiconductor random access memory device.
摘要翻译：具有用于接收多位数据的输入端子和用于发送多位数据的输出端子的半导体随机存取存储器件包括连接到多对数据线并且包括多个存储单元的存储单元矩阵。还包括地址解码器电路，其响应用于提供地址选择信号的外部地址信号和多个数据输入控制电路，用于接收多位数据的1位数据信号和1位信号，并提供作为一对互补信号，作为响应于输入到其的各种信号的多比特数据信号的1比特数据信号或1比特信号。还提供多个数据输入/输出开关电路和位数据输出控制电路以及1位数据输出电路和位信号输出控制电路，用于正确输出多位数据的1位数据或1位信号从半导体随机存取存储器件的输出。

6. 发明授权

US4417163A Buffer circuits 失效
标题翻译：缓冲电路
公开(公告)号：US4417163A
公开(公告)日：1983-11-22
申请号：US235035
申请日：1981-02-17
申请人： Yoshio Otsuki , Masaru Uesugi , Nobuaki Ieda
发明人： Yoshio Otsuki , Masaru Uesugi , Nobuaki Ieda
IPC分类号： G11C11/41 , G11C11/413 , H03K3/356 , H03K19/0185 , H03K19/092 , G11C8/00 , H03K17/693
CPC分类号： H03K3/356095 , H03K3/35606
摘要： The buffer circuit is provided with a high sensitivity balanced type flip-flop circuit and a capacative coupling provided by MOS capacitance, and a load drive circuit utilizes bootstrap effect, thus producing complementary signals having a MOS level from a TTL address input signal.
摘要翻译：缓冲电路设置有高灵敏度平衡型触发电路和由MOS电容提供的电容耦合，负载驱动电路利用自举效应，从TTL地址输入信号产生具有MOS电平的互补信号。

7. 发明授权

US5278799A Semiconductor memory circuit 失效
标题翻译：半导体存储电路
公开(公告)号：US5278799A
公开(公告)日：1994-01-11
申请号：US702329
申请日：1991-05-20
申请人： Masaru Uesugi
发明人： Masaru Uesugi
IPC分类号： G11C11/409 , G11C11/4096 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4096
摘要： A semiconductor memory circuit in which data are stored in dynamic type memory cells located at cross-points of bit and word lines, and are refreshed within a predetermined time by a sense amplifier so as to hold the thus stored data includes a first bit line connected to a first sense node of the sense amplifier. A second bit line is connected to a second sense node of the sense amplifier. A first switching circuit having a first terminal is disposed between the first bit line and the first sense node, for coupling the first bit line with the first sense node in response to a first control signal applied to the first terminal. A second switching circuit having a second terminal is disposed between the second bit line and the second sense node, for coupling the second bit line with the second sense node in response to a second control signal applied to the second terminal. A first control line is coupled to the first terminal and isolated from the second switching circuit and the second bit line, for providing the first control signal. A second control line is coupled to the second terminal and isolated from the first switching circuit and the first bit line, for providing the second control signal.
摘要翻译：一种半导体存储器电路，其中数据存储在位于位和字线的交叉点的动态类型存储单元中，并且在预定时间内被读出放大器刷新以便保持由此存储的数据包括连接的第一位线到感测放大器的第一感测节点。第二位线连接到读出放大器的第二感测节点。具有第一端子的第一开关电路设置在第一位线和第一感测节点之间，用于响应于施加到第一端子的第一控制信号而将第一位线与第一感测节点耦合。具有第二端子的第二开关电路设置在第二位线和第二感测节点之间，用于响应于施加到第二端子的第二控制信号而将第二位线与第二感测节点耦合。第一控制线耦合到第一端子并与第二开关电路和第二位线隔离，用于提供第一控制信号。第二控制线耦合到第二终端并与第一开关电路和第一位线隔离，用于提供第二控制信号。

8. 发明授权

US5216634A Semiconductor memory device 失效
公开(公告)号：US5216634A
公开(公告)日：1993-06-01
申请号：US647441
申请日：1991-01-29
申请人： Tsuneo Takano , Masaru Uesugi
发明人： Tsuneo Takano , Masaru Uesugi
IPC分类号： G11C11/409 , G11C7/10 , G11C11/401 , G11C11/41 , H01L21/8242 , H01L27/108
CPC分类号： G11C7/10 , G11C7/1006
摘要： A semiconductor memory device has pairs of complementary bit lines connected to pairs of complementary data bus lines via transfer elements controlled by column lines. The bit lines are arranged so that mutually adjacent pairs of bit lines are connected to the same pair of data bus lines at a pair of common nodes. The transfer elements for each such mutually adjacent pair of bit lines are controlled by different column lines.

9. 发明授权

US5140556A Semiconductor memory circuit having dummy cells connected to twisted bit lines 失效
标题翻译：半导体存储器电路具有连接到扭曲位线的虚设单元
公开(公告)号：US5140556A
公开(公告)日：1992-08-18
申请号：US627324
申请日：1990-12-14
申请人： Shizuo Cho , Masaru Uesugi
发明人： Shizuo Cho , Masaru Uesugi
IPC分类号： G11C7/14 , G11C7/18 , G11C11/4099
CPC分类号： G11C7/14 , G11C11/4099 , G11C7/18
摘要： A semiconductor memory circuit includes a plurality of bit line pairs each having intersecting portions where the paired bit lines intersect each other, and a plurality of pairs of memory word lines intersecting the bit lines in a direction substantially perpendicular to the bit lines. A plurality of memory cells are individually connected to the memory word lines and bit lines at intersections of one of the memory word lines of the individual memory word line pairs and one of the bit lines of the individual bit lines pairs and at intersections of the other of the paired memory word lines and the other of the paired bit lines for storing charges each being associated with data to be stored. A pair of dummy word lines are interposed between the intersecting portions of the bit lines and intersect the bit line pairs in a direction substantially perpendicular to the bit line pairs. A plurality of dumy cells are individually connected between the dummy word line pairs and the bit line pairs at intersections of one of the dummy word lines of the individual word line pairs and one of the bit lines of the individual bit line pairs and at intersections of the other of the paired dummy word lines and the other of the paired bit lines.
摘要翻译：半导体存储器电路包括多个位线对，每个位线对具有成对的位线相交的相交部分，以及与位线基本上垂直于位线的方向相交的多对存储器字线。多个存储单元分别连接到各个存储字线对的一个存储字线与各位线对中的一个位线和另一个位线的交点处的存储字线和位线的配对存储器字线和用于存储每个与要存储的数据相关联的电荷的成对位线中的另一个。一对虚拟字线插入在位线的相交部分之间，并且在与位线对基本垂直的方向上与位线对相交。多个虚拟单元分别连接在虚拟字线对和位线对之间，在各个字线对之间的一个虚拟字线和各个位线对的位线之一的交点处和配对的虚拟字线中的另一个和配对的位线中的另一个。

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