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1. 发明授权

US07655992B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07655992B2
公开(公告)日：2010-02-02
申请号：US11806462
申请日：2007-05-31
申请人： Shuichi Takahashi , Yutaka Yamada , Masaru Kanai
发明人： Shuichi Takahashi , Yutaka Yamada , Masaru Kanai
IPC分类号： H01L31/119 , H01L21/332
CPC分类号： H01L27/0629 , H01L27/0738 , H01L29/4238
摘要： The invention is directed to providing a resistor with high reliability. The invention is also directed to miniaturizing a semiconductor device having a MOS transistor and a resistor element on the same semiconductor substrate. An N-type well region is formed in a front surface of a P-type semiconductor substrate, and a P−-type resistor layer is formed in a front surface of the well region. A conductive layer is annularly formed on the well region so as to surround the resistor layer. A predetermined voltage is applied to the conductive layer and a channel is not formed under the conductive layer during normal operation, thereby isolating a pull-down resistor from the other elements (e.g. a P-channel type MOS transistor). The resistor layer and an element isolation insulation film do not contact each other. Both the PMOS and the pull-down resistor are formed in one region surrounded by the element isolation insulation film.
摘要翻译：本发明旨在提供一种具有高可靠性的电阻器。本发明还涉及在同一半导体衬底上使具有MOS晶体管和电阻元件的半导体器件小型化。在P型半导体基板的正面形成有N型阱区，在该阱区的前表面形成有P型电阻层。导电层环形地形成在阱区上，以便围绕电阻层。预定的电压被施加到导电层，并且在正常操作期间在导电层下方不形成沟道，从而将下拉电阻器与其它元件（例如P沟道型MOS晶体管）隔离。电阻层和元件隔离绝缘膜不会相互接触。 PMOS和下拉电阻都形成在由元件隔离绝缘膜包围的一个区域中。

2. 发明申请

US20070278594A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070278594A1
公开(公告)日：2007-12-06
申请号：US11806462
申请日：2007-05-31
申请人： Shuichi Takahashi , Yutaka Yamada , Masaru Kanai
发明人： Shuichi Takahashi , Yutaka Yamada , Masaru Kanai
IPC分类号： H01L29/76
CPC分类号： H01L27/0629 , H01L27/0738 , H01L29/4238
摘要： The invention is directed to providing a resistor with high reliability. The invention is also directed to miniaturizing a semiconductor device having a MOS transistor and a resistor element on the same semiconductor substrate. An N-type well region is formed in a front surface of a P-type semiconductor substrate, and a P−-type resistor layer is formed in a front surface of the well region. A conductive layer is annularly formed on the well region so as to surround the resistor layer. A predetermined voltage is applied to the conductive layer and a channel is not formed under the conductive layer during normal operation, thereby isolating a pull-down resistor from the other elements (e.g. a P-channel type MOS transistor). The resistor layer and an element isolation insulation film do not contact each other. Both the PMOS and the pull-down resistor are formed in one region surrounded by the element isolation insulation film.
摘要翻译：本发明旨在提供一种具有高可靠性的电阻器。本发明还涉及在同一半导体衬底上使具有MOS晶体管和电阻元件的半导体器件小型化。在P型半导体衬底的正面形成有N型阱区，在阱区的前表面形成有P型电阻层。导电层环形地形成在阱区上，以便围绕电阻层。预定的电压被施加到导电层，并且在正常操作期间在导电层下方不形成沟道，从而将下拉电阻器与其它元件（例如P沟道型MOS晶体管）隔离。电阻层和元件隔离绝缘膜不会相互接触。 PMOS和下拉电阻都形成在由元件隔离绝缘膜包围的一个区域中。

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