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    • 4. 发明授权
    • Cache system which performs cache flash upon emergency and dual system
    • 在紧急和双重系统上执行缓存闪存的缓存系统
    • US06829681B1
    • 2004-12-07
    • US09589390
    • 2000-06-07
    • Masao Asai
    • Masao Asai
    • G06F1200
    • G06F11/1666G06F11/20G06F12/0804G06F2201/82
    • A dual system includes a 0-subsystem and a 1-subsystem, each of which in turn includes a first bus, a second bus, a main memory having a memory section reading from and writing into which is performed over the first bus, a cache memory, a processor for outputting a first command for instruction to write back data of the cache memory into the main memory, a cache memory control section having a first reset terminal, through which an element thereof takes part in control of the first bus, for performing write back processing of data of the cache memory into the main memory based on the first command, and a system control section for controlling system changeover between an act system and a standby system over the system confounding line.
    • 双系统包括0子系统和1子系统,每个子系统又包括第一总线,第二总线,具有从第一总线读取和写入的存储器部分的主存储器,高速缓存器 存储器,用于输出用于将高速缓冲存储器的数据写回到主存储器中的指令的第一命令的处理器;具有第一复位端的高速缓存存储器控制部分,其元素通过该第一复位端子参与第一总线的控制,用于 基于第一命令执行将高速缓冲存储器的数据写回到主存储器中的系统控制部分,用于通过系统混杂线控制动作系统和备用系统之间的系统切换。