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1. 发明申请

US20100179976A1 SEMICONDUCTOR DEVICE PERFORMING OPERATIONAL PROCESSING 审中-公开
标题翻译：执行操作处理的半导体器件
公开(公告)号：US20100179976A1
公开(公告)日：2010-07-15
申请号：US12687756
申请日：2010-01-14
申请人： Masakatsu ISHIZAKI , Takeshi Kumaki , Masaharu Tagami , Yuta Imai , Tetsushi Koide , Hans Jürgen Mattausch , Takayuki Gyoten , Hideyuki Noda , Yoshihiro Okuno , Kazutami Arimoto
发明人： Masakatsu ISHIZAKI , Takeshi Kumaki , Masaharu Tagami , Yuta Imai , Tetsushi Koide , Hans Jürgen Mattausch , Takayuki Gyoten , Hideyuki Noda , Yoshihiro Okuno , Kazutami Arimoto
IPC分类号： G06F7/44 , G06F5/01 , G06F7/552
CPC分类号： G06F7/5235 , G06F7/5324 , G06F7/5338
摘要： A semiconductor device includes a decoder receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm, and a first partial product calculation unit receiving first multiplicand data of 2 bits indicating a multiplicand, a shift flag, an inversion flag, and an operation flag to select one of the higher order bit and lower order bit of the first multiplicand data based on the shift flag, invert or non-invert the selected bit based on the inversion flag, select one of the inverted or non-inverted data and data of a predetermined logic level based on the operation flag, and output the selected data as partial product data indicating the partial product of the first multiplier data and the first multiplicand data.
摘要翻译：半导体器件包括：解码器，接收根据布斯（Booth）算法的3比特的第一乘法器数据，指示乘法器输出移位标志，反转标志和操作标志，第一部分乘积计算单元接收2位的第一被乘数数据指示被乘数，移位标志，反转标志和操作标志，以基于移位标志来选择第一被乘数数据的高位位和低位位之一，基于该选择位反转或非反转所选位反转标志，基于操作标志选择反相或非反相数据和预定逻辑电平的数据之一，并将选择的数据作为指示第一乘法器数据和第一被乘数数据的部分乘积的部分乘积数据输出。

2. 发明授权

US09542190B2 Processor with fetch control for stoppage 有权
标题翻译：具有取消控制的处理器停止
公开(公告)号：US09542190B2
公开(公告)日：2017-01-10
申请号：US14378609
申请日：2012-02-14
申请人： Masakatsu Ishizaki
发明人： Masakatsu Ishizaki
IPC分类号： G06F9/38 , G06F12/08 , G06F9/30
CPC分类号： G06F9/3804 , G06F9/30058 , G06F12/0862 , G06F12/0875 , G06F12/0884 , G06F12/0888 , G06F2212/1028 , G06F2212/452 , Y02D10/13
摘要： A data processor of an embodiment includes a memory, an instruction cache, a processing unit (CPU), and a fetch process control unit. The memory stores a program in which a plurality of instructions are written. The instruction cache operates only when a branch instruction included in the program is executed, and data of a greater capacity than a width of a bus of the memory is read from the memory and stored in the instruction cache in advance. The processing unit accesses both the memory and the instruction cache and executes, in a pipelined manner, instructions read from the memory or the instruction cache. The fetch process control unit generates, in response to a branch instruction executed by the processing unit, a stop signal for stopping a fetch process of reading an instruction from the memory, and outputs the stop signal to the memory.
摘要翻译：实施例的数据处理器包括存储器，指令高速缓存，处理单元（CPU）和获取处理控制单元。存储器存储写入多个指令的程序。指令高速缓冲存储器仅在执行包含在该程序中的分支指令时进行操作，并且从存储器中读取比存储器的总线宽度更大的容量的数据，并预先存储在指令高速缓存器中。处理单元访问存储器和指令高速缓存，并以流水线的方式执行从存储器或指令高速缓存读取的指令。获取处理控制单元响应于由处理单元执行的分支指令产生用于停止从存储器读取指令的获取处理的停止信号，并将该停止信号输出到存储器。

3. 发明申请

US20150058600A1 DATA PROCESSOR 有权
标题翻译：数据处理器
公开(公告)号：US20150058600A1
公开(公告)日：2015-02-26
申请号：US14378609
申请日：2012-02-14
申请人： Masakatsu Ishizaki
发明人： Masakatsu Ishizaki
IPC分类号： G06F9/38 , G06F12/08 , G06F9/30
CPC分类号： G06F9/3804 , G06F9/30058 , G06F12/0862 , G06F12/0875 , G06F12/0884 , G06F12/0888 , G06F2212/1028 , G06F2212/452 , Y02D10/13
摘要： A data processor of an embodiment includes a memory, an instruction cache, a processing unit (CPU), and a fetch process control unit. The memory stores a program in which a plurality of instructions are written. The instruction cache operates only when a branch instruction included in the program is executed, and data of a greater capacity than a width of a bus of the memory is read from the memory and stored in the instruction cache in advance. The processing unit accesses both the memory and the instruction cache and executes, in a pipelined manner, instructions read from the memory or the instruction cache. The fetch process control unit generates, in response to a branch instruction executed by the processing unit, a stop signal for stopping a fetch process of reading an instruction from the memory, and outputs the stop signal to the memory.
摘要翻译：实施例的数据处理器包括存储器，指令高速缓存，处理单元（CPU）和获取处理控制单元。存储器存储写入多个指令的程序。指令高速缓冲存储器仅在执行包含在该程序中的分支指令时进行操作，并且从存储器中读取比存储器的总线宽度更大的容量的数据，并预先存储在指令高速缓存器中。处理单元访问存储器和指令高速缓存，并以流水线的方式执行从存储器或指令高速缓存读取的指令。获取处理控制单元响应于由处理单元执行的分支指令产生用于停止从存储器读取指令的获取处理的停止信号，并将该停止信号输出到存储器。

4. 发明授权

US07860328B2 Compression processing apparatus and compression processing method 有权
标题翻译：压缩处理装置和压缩处理方法
公开(公告)号：US07860328B2
公开(公告)日：2010-12-28
申请号：US12664946
申请日：2008-07-31
申请人： Hans Juergen Mattausch , Tetsushi Koide , Takeshi Kumaki , Masakatsu Ishizaki
发明人： Hans Juergen Mattausch , Tetsushi Koide , Takeshi Kumaki , Masakatsu Ishizaki
IPC分类号： G06K9/46
CPC分类号： H03M7/42 , H03M7/40 , H04N19/13 , H04N19/14 , H04N19/17 , H04N19/18 , H04N19/42 , H04N19/60
摘要： A dividing unit divides respective symbol sequences of input data applied with zigzag scan and a run-length process into a plurality of subsets having similar frequencies of occurrence, depending on a difference in frequencies of occurrence. A table creating unit scans each subset and creates a Huffman coding table for each subset. A coding unit executes a process for performing Huffman coding on each subset by using the Huffman coding table created for the subset, for all of the subsets in the plurality of subsets.
摘要翻译：分割单元根据发生频率的差异，将施加有锯齿形扫描和游程长度处理的输入数据的各符号序列分割为具有相似发生频率的多个子集。表创建单元扫描每个子集，并为每个子集创建霍夫曼编码表。编码单元通过使用针对该子集创建的霍夫曼编码表，对多个子集中的所有子集执行用于对每个子集执行霍夫曼编码的处理。

5. 发明申请

US20100189351A1 COMPRESSION PROCESSING APPARATUS AND COMPRESSION PROCESSING METHOD 有权
标题翻译：压缩加工设备和压缩加工方法
公开(公告)号：US20100189351A1
公开(公告)日：2010-07-29
申请号：US12664946
申请日：2008-07-31
申请人： Hans Juergen Mattausch , Tetsushi Koide , Takeshi Kumaki , Masakatsu Ishizaki
发明人： Hans Juergen Mattausch , Tetsushi Koide , Takeshi Kumaki , Masakatsu Ishizaki
IPC分类号： G06K9/34 , G06K9/36
CPC分类号： H03M7/42 , H03M7/40 , H04N19/13 , H04N19/14 , H04N19/17 , H04N19/18 , H04N19/42 , H04N19/60
摘要： A dividing unit divides respective symbol sequences of input data applied with zigzag scan and a run-length process into a plurality of subsets having similar frequencies of occurrence, depending on a difference in frequencies of occurrence. A table creating unit scans each subset and creates a Huffman coding table for each subset. A coding unit executes a process for performing Huffman coding on each subset by using the Huffman coding table created for the subset, for all of the subsets in the plurality of subsets.
摘要翻译：分割单元根据发生频率的差异，将施加有锯齿形扫描和游程长度处理的输入数据的各符号序列分割为具有相似发生频率的多个子集。表创建单元扫描每个子集，并为每个子集创建霍夫曼编码表。编码单元通过使用针对该子集创建的霍夫曼编码表，对多个子集中的所有子集执行用于对每个子集执行霍夫曼编码的处理。

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