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1. 发明申请

US20100134162A1 CLOCK SIGNAL GENERATION CIRCUIT 有权
标题翻译：时钟信号发生电路
公开(公告)号：US20100134162A1
公开(公告)日：2010-06-03
申请号：US12606666
申请日：2009-10-27
申请人： Masafumi KONDOU
发明人： Masafumi KONDOU
IPC分类号： H03L7/06 , H03K3/03
CPC分类号： H03L7/0995 , G01R31/31727 , H03K3/0315 , H03K5/133 , H03K5/1504 , H03K2005/00026 , H03L7/0812 , H03L7/0891 , H03L7/0996
摘要： A clock signal generation apparatus includes a clock signal generation circuit generating a plurality of clock signals, and a self-test circuit measuring a phase difference of one pair of clock signals. The self-test circuit includes a clock signal selection circuit selecting the pair of clock signals among the plurality of clock signals, a phase detection circuit generating a phase difference pulse signal, a test signal generation circuit generating a test signal having a frequency which is lower than the phase difference pulse signal, and a counter circuit counting the pulse number of the test signal.
摘要翻译：时钟信号发生装置包括产生多个时钟信号的时钟信号产生电路和测量一对时钟信号的相位差的自检电路。自检电路包括选择多个时钟信号中的一对时钟信号的时钟信号选择电路，产生相位差脉冲信号的相位检测电路，产生频率较低的测试信号的测试信号产生电路比相位差脉冲信号，以及对测试信号的脉冲数进行计数的计数电路。

2. 发明申请

US20050035807A1 Level down converter 有权
标题翻译：降级转换器
公开(公告)号：US20050035807A1
公开(公告)日：2005-02-17
申请号：US10870913
申请日：2004-06-21
申请人： Masafumi Kondou , Toshihiko Mori
发明人： Masafumi Kondou , Toshihiko Mori
IPC分类号： G11C8/00 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/00346 , H03K19/00369 , H03K19/018521 , H03K19/018571
摘要： A level down converter having a first inverter supplied a first power supply voltage, and outputting signals made by logical inversions of input signals, and a second inverter supplied a second power supply voltage being lower than the first power supply voltage, and outputting signals made by logical inversions of output signals from the first inverter, is provided. The first inverter contains a transistor including a gate insulation film having a first film thickness. The second inverter contains a transistor including a gate insulation film having a second film thickness which is thinner than the first film thickness.
摘要翻译：具有第一反相器的降压转换器提供第一电源电压，并输出由输入信号的逻辑反相而产生的信号，第二反相器提供低于第一电源电压的第二电源电压，并输出由提供了来自第一反相器的输出信号的逻辑反转。第一反相器包括具有第一膜厚度的栅极绝缘膜的晶体管。第二反相器包括晶体管，其包括具有比第一膜厚度薄的第二膜厚度的栅极绝缘膜。

3. 发明授权

US08008955B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08008955B2
公开(公告)日：2011-08-30
申请号：US12753471
申请日：2010-04-02
申请人： Masafumi Kondou
发明人： Masafumi Kondou
IPC分类号： H03L7/06
CPC分类号： H03L7/1974 , H03L7/087 , H03L7/093
摘要： There is provided a semiconductor device having a voltage-controlled oscillator outputting an output clock signal; N pieces of control units generating a frequency-divided clock signal by frequency-dividing the output clock signal, comparing a reference clock signal and the frequency-divided clock signal, and outputting an output signal based on a comparison result; an adder adding output signals from each of the control units; and a low-pass filter filtering an output of the adder and outputting to the voltage-controlled oscillator, wherein setting information related to a frequency division ratio made of N pieces of data cycled and supplied in a sequence in synchronization with the frequency-divided clock signal is supplied to each of the control units with initial values made different from one another and a frequency-division operation and a comparison operation are performed thereby to form a moving average filter by N pieces of control units and to reduce a quantization noise, so that occurrence of a spurious in the output clock signal can be suppressed.
摘要翻译：提供了一种具有输出输出时钟信号的压控振荡器的半导体器件; N个控制单元，通过对输出时钟信号进行分频而产生分频时钟信号，比较基准时钟信号和分频时钟信号，并根据比较结果输出输出信号; 加法器，从每个控制单元加上输出信号; 以及对加法器的输出进行滤波并对压控振荡器输出的低通滤波器，其中设置与由分频时钟同步地以顺序循环和提供的N个数据组成的分频比的信息信号以彼此不同的初始值提供给每个控制单元，并且执行分频操作和比较操作，从而由N个控制单元形成移动平均滤波器并减少量化噪声，因此可以抑制在输出时钟信号中出现杂散。

4. 发明授权

US07911252B2 Clock signal generation circuit 有权
标题翻译：时钟信号发生电路
公开(公告)号：US07911252B2
公开(公告)日：2011-03-22
申请号：US12606666
申请日：2009-10-27
申请人： Masafumi Kondou
发明人： Masafumi Kondou
IPC分类号： H03K3/00
CPC分类号： H03L7/0995 , G01R31/31727 , H03K3/0315 , H03K5/133 , H03K5/1504 , H03K2005/00026 , H03L7/0812 , H03L7/0891 , H03L7/0996
摘要： A clock signal generation apparatus includes a clock signal generation circuit generating a plurality of clock signals, and a self-test circuit measuring a phase difference of one pair of clock signals. The self-test circuit includes a clock signal selection circuit selecting the pair of clock signals among the plurality of clock signals, a phase detection circuit generating a phase difference pulse signal, a test signal generation circuit generating a test signal having a frequency which is lower than the phase difference pulse signal, and a counter circuit counting the pulse number of the test signal.
摘要翻译：时钟信号发生装置包括产生多个时钟信号的时钟信号产生电路和测量一对时钟信号的相位差的自检电路。自检电路包括选择多个时钟信号中的一对时钟信号的时钟信号选择电路，产生相位差脉冲信号的相位检测电路，产生频率较低的测试信号的测试信号产生电路比相位差脉冲信号，以及对测试信号的脉冲数进行计数的计数电路。

5. 发明申请

US20100259307A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100259307A1
公开(公告)日：2010-10-14
申请号：US12753471
申请日：2010-04-02
申请人： Masafumi Kondou
发明人： Masafumi Kondou
IPC分类号： H03L7/08
CPC分类号： H03L7/1974 , H03L7/087 , H03L7/093
摘要： There is provided a semiconductor device having a voltage-controlled oscillator outputting an output clock signal; N pieces of control units generating a frequency-divided clock signal by frequency-dividing the output clock signal, comparing a reference clock signal and the frequency-divided clock signal, and outputting an output signal based on a comparison result; an adder adding output signals from each of the control units; and a low-pass filter filtering an output of the adder and outputting to the voltage-controlled oscillator, wherein setting information related to a frequency division ratio made of N pieces of data cycled and supplied in a sequence in synchronization with the frequency-divided clock signal is supplied to each of the control units with initial values made different from one another and a frequency-division operation and a comparison operation are performed thereby to form a moving average filter by N pieces of control units and to reduce a quantization noise, so that occurrence of a spurious in the output clock signal can be suppressed.
摘要翻译：提供了一种具有输出输出时钟信号的压控振荡器的半导体器件; N个控制单元，通过对输出时钟信号进行分频而产生分频时钟信号，比较基准时钟信号和分频时钟信号，并根据比较结果输出输出信号; 加法器，从每个控制单元加上输出信号; 以及对加法器的输出进行滤波并对压控振荡器输出的低通滤波器，其中设置与由分频时钟同步地以顺序循环和提供的N个数据组成的分频比的信息信号以彼此不同的初始值提供给每个控制单元，并且执行分频操作和比较操作，从而由N个控制单元形成移动平均滤波器并减少量化噪声，因此可以抑制在输出时钟信号中出现杂散。

6. 发明授权

US07078953B2 Level down converter 有权
标题翻译：降级转换器
公开(公告)号：US07078953B2
公开(公告)日：2006-07-18
申请号：US10870913
申请日：2004-06-21
申请人： Masafumi Kondou , Toshihiko Mori
发明人： Masafumi Kondou , Toshihiko Mori
IPC分类号： H03L5/00
CPC分类号： H03K19/00346 , H03K19/00369 , H03K19/018521 , H03K19/018571
摘要： A level down converter having a first inverter supplied a first power supply voltage, and outputting signals made by logical inversions of input signals, and a second inverter supplied a second power supply voltage being lower than the first power supply voltage, and outputting signals made by logical inversions of output signals from the first inverter, is provided. The first inverter contains a transistor including a gate insulation film having a first film thickness. The second inverter contains a transistor including a gate insulation film having a second film thickness which is thinner than the first film thickness.
摘要翻译：具有第一反相器的降压转换器提供第一电源电压，并输出由输入信号的逻辑反相而产生的信号，第二反相器提供低于第一电源电压的第二电源电压，并输出由提供了来自第一反相器的输出信号的逻辑反转。第一反相器包括具有第一膜厚度的栅极绝缘膜的晶体管。第二反相器包括晶体管，其包括具有比第一膜厚度薄的第二膜厚度的栅极绝缘膜。

7. 发明授权

US08456203B2 Multiphase clock generation circuit 有权
标题翻译：多相时钟发生电路
公开(公告)号：US08456203B2
公开(公告)日：2013-06-04
申请号：US13224097
申请日：2011-09-01
申请人： Masafumi Kondou
发明人： Masafumi Kondou
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03K21/406 , H03B19/00 , H03K23/667
摘要： A multiphase clock generation circuit includes: a first frequency divider to generate a first intermediate clock and a second intermediate clock; a second frequency divider to generate output clocks of a first group including a first output clock and a second output clock; a third frequency divider to generate output clocks of a second group including a third output clock and a fourth output clock; a selector to supply one of the second intermediate clock and a value to the third frequency divider in response to a switching signal; an error detection circuit to detect an error in a phase relationship between the output clock of the first group and the output clock of the second group; and a re-reset circuit to output the switching signal to the selector based on the error.
摘要翻译：多相时钟产生电路包括：第一分频器，用于产生第一中间时钟和第二中间时钟; 第二分频器，用于产生包括第一输出时钟和第二输出时钟的第一组的输出时钟; 第三分频器，用于产生包括第三输出时钟和第四输出时钟的第二组的输出时钟; 选择器，用于响应于切换信号向第三分频器提供第二中间时钟之一和值; 检测第一组的输出时钟与第二组的输出时钟之间的相位关系的误差的误差检测电路; 以及重新设置电路，以根据该错误将切换信号输出到选择器。

8. 发明授权

US08138842B2 PLL frequency synthesizer 有权
标题翻译： PLL频率合成器
公开(公告)号：US08138842B2
公开(公告)日：2012-03-20
申请号：US12560118
申请日：2009-09-15
申请人： Masafumi Kondou , Toshihiko Mori
发明人： Masafumi Kondou , Toshihiko Mori
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/099 , H03L7/199
摘要： A frequency synthesizer includes a voltage-controlled oscillator, a frequency range tuning circuit which detects a frequency control code that sets a voltage-controlled frequency range of the voltage-controlled oscillator corresponding to the frequency division ratio which is variably-set, and a frequency control code memory which stores the frequency control code detected by the frequency range tuning circuit corresponding to the frequency division ratio. In an initialization interval, the frequency range tuning circuit detects the frequency control code corresponding to the frequency division ratio which is variably-set, and the frequency control code memory stores the frequency control code which is detected. In a normal operation interval, in response to the frequency selection signal, the frequency control code, which is stored in the frequency control code memory and corresponds to the frequency division ratio which is variably-set, is output to the voltage-controlled oscillator.
摘要翻译：频率合成器包括压控振荡器，频率范围调谐电路，其检测设置与可变设定的分频比相对应的压控振荡器的压控频率范围的频率控制码，以及频率控制代码存储器，其存储由与分频比对应的频率范围调谐电路检测的频率控制代码。在初始化间隔中，频率范围调谐电路检测与可分别设定的分频比对应的频率控制码，频率控制码存储器存储检测出的频率控制码。在正常操作间隔中，响应于频率选择信号，存储在频率控制代码存储器中并对应于可变设定的分频比的频率控制代码被输出到压控振荡器。

9. 发明申请

US20110053548A1 ELECTRICAL CIRCUIT AND RING OSCILLATOR CIRCUIT INCLUDING EVEN-NUMBER INVERTERS 有权
标题翻译：电子电路和环形振荡器电路，包括偶数变频器
公开(公告)号：US20110053548A1
公开(公告)日：2011-03-03
申请号：US12942669
申请日：2010-11-09
申请人： Masafumi KONDOU
发明人： Masafumi KONDOU
IPC分类号： H04B1/16 , H03K3/03 , H03B27/00
CPC分类号： H03K3/356113 , H03K3/0315 , H03K2005/00052 , H03K2005/00286
摘要： An electrical circuit includes a first path including even-number inverters connected in series from a first node serving as an input side to a second node serving as an output side, a second path including even-number inverters connected in series from the second node serving as an input side to the first node serving as an output side, a latch circuit providing a connection between the first node and the second node such that a logical value of the first node and a logical value of the second node are opposite to each other, and one or more control signal paths to supply one or more control signals to the latch circuit to provide and sever a connection between the latch circuit and a power supply.
摘要翻译：电路包括：第一路径，包括从用作输入侧的第一节点到用作输出侧的第二节点串联连接的偶数反相器;第二路径，包括从第二节点服务串联连接的偶数反相器作为用作输出侧的第一节点的输入侧，锁存电路，提供第一节点和第二节点之间的连接，使得第一节点的逻辑值和第二节点的逻辑值彼此相反以及一个或多个控制信号路径，以向锁存电路提供一个或多个控制信号，以提供和断开锁存电路和电源之间的连接。

10. 发明申请

US20100007425A1 PLL FREQUENCY SYNTHESIZER 有权
标题翻译： PLL频率合成器
公开(公告)号：US20100007425A1
公开(公告)日：2010-01-14
申请号：US12560118
申请日：2009-09-15
申请人： Masafumi KONDOU , Toshihiko MORI
发明人： Masafumi KONDOU , Toshihiko MORI
IPC分类号： H03L7/18
CPC分类号： H03L7/10 , H03L7/099 , H03L7/199
摘要： A frequency synthesizer includes a voltage-controlled oscillator, a frequency range tuning circuit which detects a frequency control code that sets a voltage-controlled frequency range of the voltage-controlled oscillator corresponding to the frequency division ratio which is variably-set, and a frequency control code memory which stores the frequency control code detected by the frequency range tuning circuit corresponding to the frequency division ratio. In an initialization interval, the frequency range tuning circuit detects the frequency control code corresponding to the frequency division ratio which is variably-set, and the frequency control code memory stores the frequency control code which is detected. In a normal operation interval, in response to the frequency selection signal, the frequency control code, which is stored in the frequency control code memory and corresponds to the frequency division ratio which is variably-set, is output to the voltage-controlled oscillator.
摘要翻译：频率合成器包括压控振荡器，频率范围调谐电路，其检测设置与可变设定的分频比相对应的压控振荡器的压控频率范围的频率控制码，以及频率控制代码存储器，其存储由与分频比对应的频率范围调谐电路检测的频率控制代码。在初始化间隔中，频率范围调谐电路检测与可分别设定的分频比对应的频率控制码，频率控制码存储器存储检测出的频率控制码。在正常操作间隔中，响应于频率选择信号，存储在频率控制代码存储器中并对应于可变设定的分频比的频率控制代码被输出到压控振荡器。

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