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    • 4. 发明授权
    • Memory LSI failure analysis apparatus and analysis method thereof
    • 存储器LSI故障分析装置及其分析方法
    • US06854080B2
    • 2005-02-08
    • US09819860
    • 2001-03-28
    • Mikio TanakaMasaaki Sugimoto
    • Mikio TanakaMasaaki Sugimoto
    • G01R31/28G11C29/00G11C29/44G11C29/48G11C29/54G06F11/30G11C7/00
    • G11C29/54G11C29/48
    • Provided are a device, method and storage medium, which, when a memory LSI defect analysis apparatus is used as a monitoring device to estimate reductions in yield, automatically interprets results, and calculates the period of distribution patterns and the mix rate of regular patterned defects. The total defect number of bits is found, and the factor f, is selected. The value of expected value functions, T(f), for the selected f is found, and if it is decided that regularly patterned defects are included, then regular pattern defect mix rate function MR(f) is calculated from number of bits, factor f, and the value of estimated value function T(f). If it is decided that it does not contain regularly patterned defects the regular patterned defect mix rate function MR(f) is assumed to be zero; and it is confirmed whether or not MR(f) has been found for every f.
    • 提供了一种装置,方法和存储介质,当使用存储器LSI缺陷分析装置作为估计产量降低的监测装置时,自动解释结果,并计算分布图案的周期和规则图案化缺陷的混合率 。 找到总缺陷位数,并选择因子f。 找到所选择的f的期望值函数T(f)的值,并且如果确定包括规则图案化缺陷,则从位数计算规则模式缺陷混合率函数MR(f) f和估计值函数T(f)的值。 如果确定其不包含规则图案化的缺陷,则假定规则图案化缺陷混合率函数MR(f)为零; 并且确认是否已经找到每f的MR(f)。
    • 5. 发明授权
    • Fault distribution analyzing system
    • 故障分布分析系统
    • US06493654B1
    • 2002-12-10
    • US09475067
    • 1999-12-30
    • Masaaki Sugimoto
    • Masaaki Sugimoto
    • G06F1100
    • H01L22/20G01R31/2894
    • A method of analyzing a distribution of fault elements is applied to a semiconductor integrated circuit including a plurality of elements which are repeatedly arranged in a pitch of one length unit in a specific direction. The method is accomplished by generating a position of each of fault elements in the semiconductor integrated circuit, and by performing a first determination of whether an appearance expectation function value is larger than a reference value, for each of divisors of the number of length units between fault elements, the number of length units being larger than one length unit. Also, the method is accomplished by performing a second determination of whether a distribution of the fault elements includes a regular distribution, based on the appearance expectation function value and a reference value, and by representing the determining result of the second determination.
    • 一种分析故障元件分布的方法被应用于包括沿特定方向以一个长度单位的间距重复布置的多个元件的半导体集成电路。 该方法通过在半导体集成电路中产生每个故障元件的位置,并且通过对于外观期望函数值是否大于参考值的第一确定,对于每个除数之间的长度单位数 故障元件,长度单位的数量大于一个长度单位。 此外,该方法通过基于外观期望函数值和参考值执行第二确定来确定故障元素的分布是否包括正态分布,以及通过表示第二确定的确定结果来实现。
    • 6. 发明授权
    • Apparatus and method for analyzing circuit test results and recording medium storing analytical program therefor
    • 用于分析电路测试结果的装置和方法以及存储其分析程序的记录介质
    • US06192494B1
    • 2001-02-20
    • US09095711
    • 1998-06-11
    • Masaaki Sugimoto
    • Masaaki Sugimoto
    • G11C2900
    • G01R31/318307
    • An intelligence data base 23 stores interconnection information and position information on the basis of a substrate about a decoder for an LSI memory cell and memory cells and further stores a program for judging whether the memory cell regarded as defective by a electric testing device 22 is really defective. A defect data separating computer 21 refers to the intelligence data base 23 about whether the memory cell regarded as defective by the electric testing device 22 is really defective. On this occasion, the intelligence data base 23 judges whether the memory cell in concern is truly defective and subsequently designates the memory cell's as position on the substrate according to the position information.
    • 智能数据库23基于关于LSI存储单元的解码器和存储单元的基板存储互连信息和位置信息,并且还存储用于判断由电测试装置22认为有缺陷的存储单元是否真的的程序 有缺陷 缺陷数据分离计算机21是指智能数据库23关于被电测试装置22认为有缺陷的存储单元是否真的有缺陷。 在这种情况下,智能数据库23判断所考虑的存储单元是否真正有缺陷,并随后根据位置信息将存储单元指定为基板上的位置。