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1. 发明授权

US6157994A Microprocessor employing and method of using a control bit vector storage for instruction execution 失效
标题翻译：微处理器采用和使用控制位向量存储进行指令执行的方法
公开(公告)号：US6157994A
公开(公告)日：2000-12-05
申请号：US111572
申请日：1998-07-08
申请人： Marty L. Pflum
发明人： Marty L. Pflum
IPC分类号： G06F9/30 , G06F9/38 , G06F9/312
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30167 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： A control bit vector storage is provided. The present control bit vector storage (preferably included within a functional unit) stores control bits indicative of a particular instruction. The control bits are divided into multiple control vectors, each vector indicative of one instruction operation. The control bits control dataflow elements within the functional unit to cause the instruction operation to be performed. Additionally, the present control bit vector storage allows complex instructions (or instructions which produce multiple results) to be divided into simpler operations. The hardware included within the functional unit may be reduced to that employed to perform the simpler operations. In one embodiment, the control bit vector storage comprises a plurality of vector storages. Each vector storage comprises a pair of individual vector storages and a shared vector storage. The shared vector storage stores control bits common to both control vectors.
摘要翻译：提供控制位向量存储。本控制位向量存储（优选地包括在功能单元内）存储指示特定指令的控制位。控制位分为多个控制向量，每个向量表示一个指令操作。控制位控制功能单元内的数据流元件以使得指令操作被执行。此外，本控制位向量存储允许将复杂指令（或产生多个结果的指令）分割成更简单的操作。包括在功能单元内的硬件可以减少到用于执行更简单操作的硬件。在一个实施例中，控制比特向量存储包括多个向量存储器。每个矢量存储器包括一对单独的矢量存储器和共享矢量存储器。共享矢量存储存储两个控制矢量共同的控制位。

2. 发明授权

US5903910A Method for transferring data between a pair of caches configured to be accessed from different stages of an instruction processing pipeline 失效
标题翻译：用于在配置成从指令处理流水线的不同阶段被访问的一对缓存之间传送数据的方法
公开(公告)号：US5903910A
公开(公告)日：1999-05-11
申请号：US561073
申请日：1995-11-20
申请人： Thang M. Tran , Marty L. Pflum , David B. Witt , William M. Johnson
发明人： Thang M. Tran , Marty L. Pflum , David B. Witt , William M. Johnson
IPC分类号： G06F9/30 , G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/30167 , G06F12/0875 , G06F9/30163 , G06F9/3824 , G06F9/3867
摘要： A microprocessor including a pair of caches is provided. One of the pair of caches is accessed by stack-relative memory accesses from the decode stage of the instruction processing pipeline. The second of the pair of caches is accessed by memory accesses from the execute stage of the instruction processing pipeline. When a miss is detected in the first of the pair of caches, the stack-relative memory access which misses is conveyed to the execute stage of the instruction processing pipeline. When the stack-relative memory access accesses the second of the pair of caches, the cache line containing the access is transmitted to the first of the pair of caches for storage. The first of the pair of caches selects a victim line for replacement when the data is transferred from the second of the pair of caches. If the victim line has been modified while stored in the first cache, then the victim line is stored in a copyback buffer. A signal is asserted by the first cache to inform the second cache of the need to perform a victim line copyback. Requests from the execute stage of the instruction processing pipeline are stalled to allow the copyback to occur.
摘要翻译：提供了包括一对高速缓存的微处理器。一对缓存中的一个通过来自指令处理流水线的解码级的堆栈相对存储器访问进行访问。该对高速缓存中的第二个由指令处理流水线的执行阶段的存储器访问访问。当在一对高速缓存中的第一个中检测到未命中时，丢失的堆栈相对存储器访问被传送到指令处理流水线的执行阶段。当堆栈相对存储器访问访问该对高速缓存中的第二个时，包含访问的高速缓存行被发送到该对高速缓存中的第一个用于存储。一对缓存中的第一个在从一对缓存中的第二个数据传输数据时选择一个受害者行进行替换。如果受害者行已被存储在第一个缓存中被修改，那么受害者行将被存储在一个副本缓冲区中。一个信号由第一个缓存断言，通知第二个缓存是否需要执行受害线回拷。来自指令处理流水线的执行阶段的请求被停止以允许发生回拷。

3. 发明授权

US5822560A Apparatus for efficient instruction execution via variable issue and variable control vectors per issue 失效
标题翻译：用于通过每个问题的可变问题和可变控制向量有效执行指令的设备
公开(公告)号：US5822560A
公开(公告)日：1998-10-13
申请号：US652785
申请日：1996-05-23
申请人： Marty L. Pflum
发明人： Marty L. Pflum
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3017 , G06F9/30167 , G06F9/382 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857
摘要： An apparatus employs a flexible instruction categorization scheme which includes three categories: single dispatch, multiple dispatch, and microcode. Single dispatch instructions are performed in one functional unit. Conversely, multiple dispatch instructions are conveyed to multiple functional units, each of which perform a portion of the multiple dispatch instruction. A predefined fixed number of functional units are employed to execute a multiple dispatch instruction, allowing for additional instructions to be dispatched concurrently with the multiple dispatch instructions. In contrast to multiple dispatch instructions, microcode instructions may occupy a variable number of functional units and may dispatch instructions for a variable number of clock cycles. Additionally, multiple instruction operations may be performed in a given functional unit in response to an instruction. In one embodiment, up to two instruction operations may be performed in a functional unit. The instruction operations corresponding to a particular instruction are stored as control vectors in a control vector storage within the corresponding functional unit.
摘要翻译：一种装置采用灵活的指令分类方案，其中包括三类：单一调度，多调度和微码。单个调度指令在一个功能单元中执行。相反，多个调度指令被传送到多个功能单元，每个功能单元执行多个调度指令的一部分。使用预定义的固定数量的功能单元来执行多个分派指令，允许与多个调度指令同时调度附加指令。与多个调度指令相反，微代码指令可以占用可变数量的功能单元，并且可以为可变数量的时钟周期分派指令。此外，响应于指令，可以在给定功能单元中执行多个指令操作。在一个实施例中，可以在功能单元中执行最多两个指令操作。对应于特定指令的指令操作作为控制向量存储在对应的功能单元内的控制向量存储器中。

4. 发明授权

US09038480B2 Integrated circuit and apparatus for detecting oscillations 有权
标题翻译：用于检测振荡的集成电路和装置
公开(公告)号：US09038480B2
公开(公告)日：2015-05-26
申请号：US13342506
申请日：2012-01-03
申请人： Marty L. Pflum , Michael Keith Odland , Kenneth W. Fernald
发明人： Marty L. Pflum , Michael Keith Odland , Kenneth W. Fernald
IPC分类号： G01F1/20 , G01F1/716 , G01F1/115 , G01F1/075 , G01D4/00
CPC分类号： G01F1/115 , G01D4/00 , G01F1/075
摘要： An integrated circuit includes a pulse generator to provide an excitation pulse to an output terminal and a comparator to receive a signal in response to the excitation pulse and for comparing the signal to a threshold to produce a comparator output signal corresponding to oscillations in the signal. The integrated circuit further includes a counter to count pulses in the comparator output signal and a discriminator circuit to compare a count value of the counter to a damping threshold and for providing an output signal having a first value when the count value is equal to or exceeds the damping threshold and otherwise having a second value.
摘要翻译：集成电路包括：脉冲发生器，用于向输出端提供激励脉冲;以及比较器，用于响应激励脉冲接收信号，并将信号与阈值进行比较，以产生与信号中的振荡相对应的比较器输出信号。集成电路还包括对比较器输出信号中的计数脉冲的计数器和鉴别器电路，用于将计数器的计数值与阻尼阈值进行比较，并且当计数值等于或超过时，提供具有第一值的输出信号阻尼阈值，否则具有第二值。

5. 发明授权

US06351804B1 Control bit vector storage for a microprocessor 有权
标题翻译：控制微处理器的位向量存储
公开(公告)号：US06351804B1
公开(公告)日：2002-02-26
申请号：US09685987
申请日：2000-10-10
申请人： Marty L. Pflum
发明人： Marty L. Pflum
IPC分类号： G06F930
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30167 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： A control bit vector storage is provided. The present control bit vector storage (preferably included within a functional unit) stores control bits indicative of a particular instruction. The control bits are divided into multiple control vectors, each vector indicative of one instruction operation. The control bits control dataflow elements within the functional unit to cause the instruction operation to be performed. Additionally, the present control bit vector storage allows complex instructions (or instructions which produce multiple results) to be divided into simpler operations. The hardware included within the functional unit may be reduced to that employed to perform the simpler operations. In one embodiment, the control bit vector storage comprises a plurality of vector storages. Each vector storage comprises a pair of individual vector storages and a shared vector storage. The shared vector storage stores control bits common to both control vectors.
摘要翻译：提供控制位向量存储。本控制位向量存储（优选地包括在功能单元内）存储指示特定指令的控制位。控制位分为多个控制向量，每个向量表示一个指令操作。控制位控制功能单元内的数据流元件以使得指令操作被执行。此外，本控制位向量存储允许将复杂指令（或产生多个结果的指令）分割成更简单的操作。包括在功能单元内的硬件可以减少到用于执行更简单操作的硬件。在一个实施例中，控制比特向量存储包括多个向量存储器。每个矢量存储器包括一对单独的矢量存储器和共享矢量存储器。共享矢量存储存储两个控制矢量共同的控制位。

6. 发明授权

US5787474A Dependency checking structure for a pair of caches which are accessed from different pipeline stages of an instruction processing pipeline 失效
标题翻译：用于从指令处理流水线的不同流水线阶段访问的一对高速缓存的依赖性检查结构
公开(公告)号：US5787474A
公开(公告)日：1998-07-28
申请号：US561033
申请日：1995-11-20
申请人： Marty L. Pflum
发明人： Marty L. Pflum
IPC分类号： G06F9/38 , G06F12/08 , G06F13/00
CPC分类号： G06F12/0848 , G06F12/0875 , G06F9/3834 , G06F9/3838
摘要： A pair of caches having a dependency checking structure for accesses between them is provided. One of the pair of caches is accessed from the decode stage of the instruction processing pipeline, while the other is accessed from the execute stage. The dependency checking structure monitors for memory dependencies between accesses to each of the pair of caches. Memory accesses may be performed earlier in the instruction processing pipeline than was previously achievable. Additionally, the dependency checking structure ensures that memory accesses receive the correct data by comparing accesses performed from each stage of the instruction processing pipeline to each other. In one embodiment, read and write dependency bits are stored by the cache which is accessed from the decode stage of the instruction processing pipeline. Decode stage accesses are recorded as a read or write by setting an associated dependency bit. When accesses are performed from the execute stage, the dependency bits are checked to determine if a dependency exists with respect to an access performed from the decode stage. Corrective actions are performed based on analysis of the dependency bits. Correct results are maintained for the cases in which dependencies exist by effectively forcing the accesses to occur in program order.
摘要翻译：提供了一对具有用于它们之间的访问的依赖关系检查结构的高速缓存。从指令处理流水线的解码阶段访问一对高速缓存中的一个，另一个从执行阶段进行访问。依赖关系检查结构监视对一对缓存中的每一个的访问之间的存储器依赖性。可以在指令处理流水线中较早地执行存储器访问，而不是先前可实现的。此外，依赖性检查结构确保存储器访问通过将从指令处理流水线的各个阶段执行的访问相互比较来接收正确的数据。在一个实施例中，读取和写入相关性位由从指令处理流水线的解码级访问的高速缓存存储。解码级访问通过设置关联的依赖位来记录为读或写。当从执行阶段执行访问时，检查相关性位以确定是否存在关于从解码级执行的访问的依赖关系。基于依赖位的分析来执行纠正措施。通过有效地强制访问以程序顺序发生，存在依赖关系的情况下保持正确的结果。

7. 发明授权

US5768610A Lookahead register value generator and a superscalar microprocessor employing same 失效
标题翻译：前瞻寄存器值发生器和采用其的超标量微处理器
公开(公告)号：US5768610A
公开(公告)日：1998-06-16
申请号：US480092
申请日：1995-06-07
申请人： Marty L. Pflum
发明人： Marty L. Pflum
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3806 , G06F9/3004 , G06F9/30149 , G06F9/3816 , G06F9/3826 , G06F9/383 , G06F9/3832 , G06F9/3848 , G06F9/3861
摘要： A lookahead register value generator is provided which is configured to maintain lookahead values for registers with respect to instructions decoded in prior clock cycles. Each clock cycle, an instruction having one of these registers and an operand may receive a corresponding operand value generated using the values stored in these lookahead registers while the associated instruction is in the decode stage of the instruction processing pipeline. If the operand value is an address, the value may be used to fetch operand data residing at the address before the instruction arrives in the execute stage of the instruction processing pipeline. Additionally, the lookahead register value generator generates operand values for a second instruction which is dependent upon a concurrently decoded first instruction, thereby removing the dependency therebetween. Instructions for which the values are generated may execute concurrently, as opposed to serially executing.
摘要翻译：提供了一个前瞻寄存器值产生器，其被配置为相对于在先前的时钟周期中解码的指令来保持寄存器的前端值。每个时钟周期，具有这些寄存器之一的指令和操作数可以接收使用存储在这些前瞻寄存器中的值而生成的对应操作数值，同时相关联的指令处于指令处理流水线的解码阶段。如果操作数值是一个地址，则该值可以用于在指令到达指令处理流水线的执行阶段之前获取驻留在地址处的操作数数据。此外，前瞻寄存器值生成器生成依赖于同时解码的第一指令的第二指令的操作数值，从而消除它们之间的依赖关系。生成值的指令可以并发执行，而不是连续执行。

8. 发明授权

US5831462A Conditional latching mechanism and pipelined microprocessor employing the same 失效
标题翻译：条件闭锁机构和采用其的流水线微处理器
公开(公告)号：US5831462A
公开(公告)日：1998-11-03
申请号：US744707
申请日：1996-10-31
申请人： David B. Witt , Marty L. Pflum
发明人： David B. Witt , Marty L. Pflum
IPC分类号： G06F9/38 , H03K3/037
CPC分类号： G06F9/3869 , H03K3/037
摘要： A conditional latch circuit is provided wherein a first transmission gate is electrically coupled in series with a second transmission gate between an input node and an output node. The latch circuit is controlled by a conditional clock signal wherein a delay element is employed to cause both transmission gates to be simultaneously enabled upon an edge of the conditional clock signal. The length of time during which both transmission gates are enabled is determined by an electrical delay associated with the delay element. When both transmission gates are enabled, the input node is electrically coupled to the output node. A keeper circuit at the output of the second transmission gate retains a logical value at the output of the latch after the input node is decoupled from the output line by disabling the first transmission gate. An edge of the conditional clock signal which causes a new input value to be latched within the latch circuit is driven by a logic gate which receives a clock signal at a first input, a condition signal at a second input, and an inhibit signal at a third input. The inhibit signal is provided from an inhibit signal generator and is provided to prevent the false-firing of the latch if the condition signal is asserted while the clock signal is active.
摘要翻译：提供了一种条件锁存电路，其中第一传输门与输入节点和输出节点之间的第二传输门电路串联电耦合。锁存电路由条件时钟信号控制，其中使用延迟元件以使得在条件时钟信号的边缘上同时使能传输门。两个传输门被使能的时间长度由与延迟元件相关联的电延迟确定。当两个传输门被使能时，输入节点电耦合到输出节点。在第二传输门的输出处的保持器电路在通过禁用第一传输门而在输入节点与输出线路去耦之后，在锁存器的输出处保留逻辑值。使得新的输入值被锁存在锁存电路内的条件时钟信号的边缘由逻辑门驱动，该逻辑门在第一输入端接收时钟信号，在第二输入端接收时钟信号，在第二输入端接收禁止信号第三输入。禁止信号由禁止信号发生器提供，并被提供以防止在时钟信号有效时条件信号被断言时锁存器的假发射。

9. 发明授权

US5813033A Superscalar microprocessor including a cache configured to detect dependencies between accesses to the cache and another cache 失效
标题翻译：超标量微处理器包括被配置为检测对高速缓存的访问和另一高速缓存之间的依赖性的缓存
公开(公告)号：US5813033A
公开(公告)日：1998-09-22
申请号：US612537
申请日：1996-03-08
申请人： Marty L. Pflum
发明人： Marty L. Pflum
IPC分类号： G06F9/30 , G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/30152 , G06F12/0848 , G06F9/3816 , G06F9/382 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A microprocessor is provided including a pair of caches and a dependency checking structure for accesses between the pair of caches. One of the pair of caches is accessed from the decode stage of the instruction processing pipeline, while the other is accessed from the execute stage. The dependency checking structure monitors for memory dependencies between accesses to each of the pair of caches. Memory accesses may be performed earlier in the instruction processing pipeline than was previously achievable. Additionally, the dependency checking structure ensures that memory accesses receive the correct data by comparing accesses performed from each stage of the instruction processing pipeline to each other. In one embodiment, read and write dependency bits are stored by the cache which is accessed from the decode stage of the instruction processing pipeline. Decode stage accesses are recorded as a read or write by setting an associated dependency bit. When accesses are performed from the execute stage, the dependency bits are checked to determine if a dependency exists with respect to an access performed from the decode stage. Corrective actions are performed based on analysis of the dependency bits. Correct results are maintained for the cases in which dependencies exist by effectively forcing the accesses to occur in program order.
摘要翻译：提供了一个微处理器，包括一对高速缓存和用于一对高速缓存之间的访问的依赖性检查结构。从指令处理流水线的解码阶段访问一对高速缓存中的一个，另一个从执行阶段进行访问。依赖关系检查结构监视对一对缓存中的每一个的访问之间的存储器依赖性。可以在指令处理流水线中较早地执行存储器访问，而不是先前可实现的。此外，依赖性检查结构确保存储器访问通过将从指令处理流水线的各个阶段执行的访问相互比较来接收正确的数据。在一个实施例中，读取和写入相关性位由从指令处理流水线的解码级访问的高速缓存存储。解码级访问通过设置关联的依赖位来记录为读或写。当从执行阶段执行访问时，检查相关性位以确定是否存在关于从解码级执行的访问的依赖关系。基于依赖位的分析来执行纠正措施。通过有效地强制访问以程序顺序发生，存在依赖关系的情况下保持正确的结果。

10. 发明授权

US5790821A Control bit vector storage for storing control vectors corresponding to instruction operations in a microprocessor 失效
标题翻译：用于存储与微处理器中的指令操作相对应的控制向量的控制位向量存储
公开(公告)号：US5790821A
公开(公告)日：1998-08-04
申请号：US612536
申请日：1996-03-08
申请人： Marty L. Pflum
发明人： Marty L. Pflum
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30167 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： A control bit vector storage is provided. The present control bit vector storage (preferably included within a functional unit) stores control bits indicative of a particular instruction. The control bits are divided into multiple control vectors, each vector indicative of one instruction operation. The control bits control dataflow elements within the functional unit to cause the instruction operation to be performed. Additionally, the present control bit vector storage allows complex instructions (or instructions which produce multiple results) to be divided into simpler operations. The hardware included within the functional unit may be reduced to that employed to perform the simpler operations. In one embodiment, the control bit vector storage comprises a plurality of vector storages. Each vector storage comprises a pair of individual vector storages and a shared vector storage. The shared vector storage stores control bits common to both control vectors.
摘要翻译：提供控制位向量存储。本控制位向量存储（优选地包括在功能单元内）存储指示特定指令的控制位。控制位分为多个控制向量，每个向量表示一个指令操作。控制位控制功能单元内的数据流元件以使得指令操作被执行。此外，本控制位向量存储允许将复杂指令（或产生多个结果的指令）分割成更简单的操作。包括在功能单元内的硬件可以减少到用于执行更简单操作的硬件。在一个实施例中，控制比特向量存储包括多个向量存储器。每个矢量存储器包括一对单独的矢量存储器和共享矢量存储器。共享矢量存储存储两个控制矢量共同的控制位。

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