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1. 发明授权

US07839168B2 Circuit with parallel functional circuits with multi-phase control inputs 有权
标题翻译：具有多相控制输入并联功能电路的电路
公开(公告)号：US07839168B2
公开(公告)日：2010-11-23
申请号：US12518696
申请日：2007-12-10
申请人： Paul Wielage , Martinus T. Bennebroek
发明人： Paul Wielage , Martinus T. Bennebroek
IPC分类号： H03K19/173
CPC分类号： G11C19/287 , G06F9/3869
摘要： A circuit has a plurality of functional circuits (100a-f), each with multiphase control inputs. A control circuit drives the inputs for each phase in parallel. The control circuit (120a-c) comprises a chain of one-shot circuits (120a-c), each comprising a bi-stable circuit (121). The bi-stable circuit (121) of a first one-shot circuit in the chain has a set input coupled to the basic control signal input (126), the bi-stable circuits (121) of a remaining or each remaining one-shot circuit (120a-c) in the chain have a set input output of its predecessor in the chain. Each bi-stable circuit (121) has an output coupled to a respective one of the multiphase control outputs (14a-c) and a reset input coupled to the respective one of the multiphase control outputs (14a-c). Loading of the multiphase control outputs (14a-c) by the functional circuits results in a delay of the reset. Thus the pulse durations of the one shot circuits are adapted to the number of functional circuits to ensure sufficient signal development.
摘要翻译：电路具有多个功能电路（100a-f），每个具有多相控制输入。控制电路并联驱动每相的输入。控制电路（120a-c）包括一个单触发电路链（120a-c），每条链包括双稳电路（121）。链中的第一单触发电路的双稳态电路（121）具有耦合到基本控制信号输入（126）的设置输入，剩余或每个剩余单次触发的双稳态电路（121）链路中的电路（120a-c）具有其前身在链中的设定输入输出。每个双稳态电路（121）具有耦合到多相控制输出（14a-c）中的相应一个的输出和耦合到多相控制输出（14a-c）中的相应一个的复位输入。通过功能电路加载多相控制输出（14a-c）会导致复位延迟。因此，单触发电路的脉冲持续时间适应于功能电路的数量，以确保足够的信号发展。

2. 发明授权

US08076955B2 Configurable logic device 有权
公开(公告)号：US08076955B2
公开(公告)日：2011-12-13
申请号：US13032542
申请日：2011-02-22
申请人： Alexander A. Danilin , Martinus T. Bennebroek , Sergei V. Sawitzki
发明人： Alexander A. Danilin , Martinus T. Bennebroek , Sergei V. Sawitzki
IPC分类号： H03K19/173 , G06F17/10
CPC分类号： G06F15/7867 , H03K19/17728
摘要： The configurable logic device comprises a plurality of configurable logic cells (2). A configurable logic cell comprises a plurality of multi-bit registers (20a, 20b, 20c, 20d). At least one is accessible both in a parallel and in a serial fashion. A functional unit (30) therein is coupled to two or more of the registers and comprises a chain of functional unit segments (31, 31′) that each comprise an AND gate (33) and a 1-bit full adder (32) receiving an output of the AND-gate. An output selection facility (50) provides an output signal of the configurable logic cell selected from two or more input signals. At least one of the input signals is provided by one of the multi-bit registers, and another by the functional unit.

3. 发明授权

US07982495B2 Configurable logic device 有权
标题翻译：可配置逻辑器件
公开(公告)号：US07982495B2
公开(公告)日：2011-07-19
申请号：US12310465
申请日：2007-08-22
申请人： Alexander A. Danilin , Martinus T. Bennebroek , Sergei V. Sawitzki
发明人： Alexander A. Danilin , Martinus T. Bennebroek , Sergei V. Sawitzki
IPC分类号： H03K19/173 , G06F17/50
CPC分类号： G06F15/7867 , H03K19/17728
摘要： The configurable logic device comprises a plurality of configurable logic cells (2). A configurable logic cell comprises a plurality of multi-bit registers (20a, 20b, 20c, 20d). At least one is accessible both in a parallel and in a serial fashion. A functional unit (30) therein is coupled to two or more of the registers and comprises a chain of functional unit segments (31, 31′) that each comprise an AND gate (33) and a 1-bit full adder (32) receiving an output of the AND-gate. An output selection facility (50) provides an output signal of the configurable logic cell selected from two or more input signals. At least one of the input signals is provided by one of the multi-bit registers, and another by the functional unit.
摘要翻译：可配置逻辑器件包括多个可配置逻辑单元（2）。可配置逻辑单元包括多个多位寄存器（20a，20b，20c，20d）。至少一个可以并行和串行的方式访问。其中的功能单元（30）耦合到两个或更多个寄存器，并且包括一系列功能单元段（31,31'），每个链包括与门（33）和1位全加器（32），其接收 AND门的输出。输出选择装置（50）提供从两个或更多个输入信号中选择的可配置逻辑单元的输出信号。至少一个输入信号由多位寄存器之一提供，另一个由功能单元提供。

4. 发明授权

US07927966B2 Method of manufacturing openings in a substrate, a via in substrate, and a semiconductor device comprising such a via 有权
标题翻译：衬底中的开口的制造方法，衬底中的通孔以及包括这种通孔的半导体器件
公开(公告)号：US07927966B2
公开(公告)日：2011-04-19
申请号：US12518684
申请日：2007-12-10
申请人： Viet Nguyen Hoang , Martinus T. Bennebroek
发明人： Viet Nguyen Hoang , Martinus T. Bennebroek
IPC分类号： H01L21/3065
CPC分类号： H01L21/76898 , H01L21/3083 , H01L23/481 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： The invention relates to a method of manufacturing openings in a substrate (5), the method comprising steps of: providing the substrate (5) with a masking layer (40) on a surface thereof; forming a first opening (10), a second opening (30), and a channel (20) in between the first opening (10) and the second opening (30) in the masking layer (40), the channel (20) connecting the first opening (10) with the second opening (30), the second opening (30) having an area (A2) that is larger than the area (A1) of the first opening (10); forming trenches (11, 21, 31) in the substrate (5) located at the first opening (10), the second opening (30), and at the channel (20) under masking of the masking layer (40) by means of anisotropic dry etching, and sealing off the trench (21) located at the channel (20) for forming the openings in the substrate (5). The method of the invention enables formation of a deeper first opening (10) than what is possible with the known methods. The invention further relates to a method of manufacturing a via in a substrate (5), which may be advantageously used in 3-dimensional integrated circuits.
摘要翻译：本发明涉及一种在衬底（5）中制造开口的方法，所述方法包括以下步骤：在其表面上为衬底（5）提供掩模层（40）; 在所述掩蔽层（40）中形成第一开口（10），第二开口（30）和位于所述第一开口（10）和所述第二开口（30）之间的通道（20），所述通道（20）连接具有第二开口（30）的第一开口（10），第二开口（30）具有比第一开口（10）的区域（A1）大的区域（A2）; 在位于第一开口（10）的第一开口（10），第二开口（30）和通道（20）处，在屏蔽层（40）的掩蔽下，在衬底（5）内形成沟槽（11,21,31），借助于各向异性干蚀刻，以及密封位于通道（20）处的沟槽（21），以形成衬底（5）中的开口。本发明的方法能够形成比已知方法可能的更深的第一开口（10）。本发明还涉及在衬底（5）中制造通孔的方法，其可有利地用于三维集成电路中。

5. 发明授权

US07795912B2 Circuit comprising a matrix of programmable logic cells 有权
标题翻译：电路包括可编程逻辑单元的矩阵
公开(公告)号：US07795912B2
公开(公告)日：2010-09-14
申请号：US12521977
申请日：2007-12-31
申请人： Alexander A. Danilin , Martinus T. Bennebroek
发明人： Alexander A. Danilin , Martinus T. Bennebroek
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737
摘要： An integrated circuit comprises a matrix (10) of programmable cells (100). Each particular one of the programmable cells (100) comprises a programmable logic circuit (22) and a bank (24) of routing multiplexers (25a-d). Each routing multiplexer (25a-d) in the bank (24) has a set of inputs connected to connections selected from a group consisting of connections to an output of the programmable logic circuit (22) and connections dedicated to outputs of routing multiplexers (25a-d) in further ones of the programmable cells (100) other than the particular one of the programmable cells (100). The further ones of the programmable cells (100) the inputs of the routing multiplexer (25a-d) in the bank (24) are connected to are positioned relative to the particular one of the programmable cells (100) in the matrix (10) in neighboring cells (100) of the particular one of the programmable cells (100) and in cells (100) beyond the neighboring cells (100).
摘要翻译：集成电路包括可编程单元（100）的矩阵（10）。每个特定的可编程单元（100）包括可编程逻辑电路（22）和布线多路复用器（25a-d）的组（24）。存储体（24）中的每个路由多路复用器（25a-d）具有一组输入，其连接到从由可编程逻辑电路（22）的输出的连接组成的组中的连接以及专用于路由多路复用器（25a）的输出的连接 -d）在可编程单元（100）中的其他可编程单元（100）中，而不是可编程单元（100）中的特定可编程单元。连接到存储体（24）中的路由多路复用器（25a-d）的输入端的另一个可编程单元（100）相对于矩阵（10）中的可编程单元（100）中的特定一个定位，在特定一个可编程单元（100）的相邻单元（100）中以及在相邻单元（100）之外的单元（100）中。

6. 发明申请

US20100085076A1 CIRCUIT COMPRISING A MATRIX OF PROGRAMMABLE LOGIC CELLS 有权
标题翻译：包含可编程逻辑单元矩阵的电路
公开(公告)号：US20100085076A1
公开(公告)日：2010-04-08
申请号：US12521977
申请日：2007-12-31
申请人： Alexander A. Danilin , Martinus T. Bennebroek
发明人： Alexander A. Danilin , Martinus T. Bennebroek
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737
摘要： An integrated circuit comprises a matrix (10) of programmable cells (100). Each particular one of the programmable cells (100) comprises a programmable logic circuit (22) and a bank (24) of routing multiplexers (25a-d). Each routing multiplexer (25a-d) in the bank (24) has a set of inputs connected to connections selected from a group consisting of connections to an output of the programmable logic circuit (22) and connections dedicated to outputs of routing multiplexers (25a-d) in further ones of the programmable cells (100) other than the particular one of the programmable cells (100). The further ones of the programmable cells (100) the inputs of the routing multiplexer (25a-d) in the bank (24) are connected to are positioned relative to the particular one of the programmable cells (100) in the matrix (10) in neighboring cells (100) of the particular one of the programmable cells (100) and in cells (100) beyond the neighboring cells (100).
摘要翻译：集成电路包括可编程单元（100）的矩阵（10）。每个特定的可编程单元（100）包括可编程逻辑电路（22）和布线多路复用器（25a-d）的组（24）。存储体（24）中的每个路由多路复用器（25a-d）具有一组输入，其连接到从由可编程逻辑电路（22）的输出的连接组成的组中的连接以及专用于路由多路复用器（25a）的输出的连接 -d）在可编程单元（100）中的其他可编程单元（100）中，而不是可编程单元（100）中的特定可编程单元。连接到存储体（24）中的路由多路复用器（25a-d）的输入端的另一个可编程单元（100）相对于矩阵（10）中的可编程单元（100）中的特定一个定位，在特定一个可编程单元（100）的相邻单元（100）中以及在相邻单元（100）之外的单元（100）中。

7. 发明申请

US20100059894A1 METHOD OF MANUFACTURING OPENINGS IN A SUBSTRATE, A VIA IN SUBSTRATE, AND A SEMICONDUCTOR DEVICE COMPRISING SUCH A VIA 有权
标题翻译：在衬底中制造开口的方法，衬底中的透明性以及包含这种威盛的半导体器件
公开(公告)号：US20100059894A1
公开(公告)日：2010-03-11
申请号：US12518684
申请日：2007-12-10
申请人： Viet Nguyen Hoang , Martinus T. Bennebroek
发明人： Viet Nguyen Hoang , Martinus T. Bennebroek
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/3083 , H01L23/481 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： The invention relates to a method of manufacturing openings in a substrate (5), the method comprising steps of: providing the substrate (5) with a masking layer (40) on a surface thereof; forming a first opening (10), a second opening (30), and a channel (20) in between the first opening (10) and the second opening (30) in the masking layer (40), the channel (20) connecting the first opening (10) with the second opening (30), the second opening (30) having an area (A2) that is larger than the area (A1) of the first opening (10); forming trenches (11, 21, 31) in the substrate (5) located at the first opening (10), the second opening (30), and at the channel (20) under masking of the masking layer (40) by means of anisotropic dry etching, and sealing off the trench (21) located at the channel (20) for forming the openings in the substrate (5). The method of the invention enables formation of a deeper first opening (10) than what is possible with the known methods. The invention further relates to a method of manufacturing a via in a substrate (5), which may be advantageously used in 3-dimensional integrated circuits.
摘要翻译：本发明涉及一种在衬底（5）中制造开口的方法，所述方法包括以下步骤：在其表面上为衬底（5）提供掩模层（40）; 在所述掩蔽层（40）中形成第一开口（10），第二开口（30）和位于所述第一开口（10）和所述第二开口（30）之间的通道（20），所述通道（20）连接具有第二开口（30）的第一开口（10），第二开口（30）具有比第一开口（10）的区域（A1）大的区域（A2）; 在位于第一开口（10）的第一开口（10），第二开口（30）和通道（20）处，在屏蔽层（40）的掩蔽下，在衬底（5）内形成沟槽（11,21,31），借助于各向异性干蚀刻，以及密封位于通道（20）处的沟槽（21），以形成衬底（5）中的开口。本发明的方法能够形成比已知方法可能的更深的第一开口（10）。本发明还涉及在衬底（5）中制造通孔的方法，其可有利地用于三维集成电路中。

8. 发明申请

US20110140735A1 CONFIGURABLE LOGIC DEVICE 有权
标题翻译：可配置逻辑器件
公开(公告)号：US20110140735A1
公开(公告)日：2011-06-16
申请号：US13032542
申请日：2011-02-22
申请人： Alexander A. Danilin , Martinus T. Bennebroek , Sergei V. Sawitzki
发明人： Alexander A. Danilin , Martinus T. Bennebroek , Sergei V. Sawitzki
IPC分类号： H03K19/173
CPC分类号： G06F15/7867 , H03K19/17728
摘要： The configurable logic device comprises a plurality of configurable logic cells (2). A configurable logic cell comprises a plurality of multi-bit registers (20a, 20b, 20c, 2Od). At least one is accessible both in a parallel and in a serial fashion. A functional unit (30) therein is coupled to two or more of the registers and comprises a chain of functional unit segments (31, 31′) that each comprise an AND gate (33) and a 1-bit full adder (32) receiving an output of the AND-gate. An output selection facility (50) provides an output signal of the configurable logic cell selected from two or more input signals. At least one of the input signals is provided by one of the multi-bit registers, and another by the functional unit.
摘要翻译：可配置逻辑器件包括多个可配置逻辑单元（2）。可配置逻辑单元包括多个多位寄存器（20a，20b，20c，20d）。至少一个可以并行和串行的方式访问。其中的功能单元（30）耦合到两个或更多个寄存器，并且包括一系列功能单元段（31,31'），每个链包括与门（33）和1位全加器（32），其接收 AND门的输出。输出选择装置（50）提供从两个或更多个输入信号中选择的可配置逻辑单元的输出信号。至少一个输入信号由多位寄存器之一提供，另一个由功能单元提供。

9. 发明申请

US20100097098A1 CONFIGURABLE LOGIC DEVICE 有权
标题翻译：可配置逻辑器件
公开(公告)号：US20100097098A1
公开(公告)日：2010-04-22
申请号：US12310465
申请日：2007-08-22
申请人： Alexander A. Danilin , Martinus T. Bennebroek , Sergei V. Sawitzki
发明人： Alexander A. Danilin , Martinus T. Bennebroek , Sergei V. Sawitzki
IPC分类号： H03K19/173
CPC分类号： G06F15/7867 , H03K19/17728
摘要： The configurable logic device comprises a plurality of configurable logic cells (2). A configurable logic cell comprises a plurality of multi-bit registers (20a, 20b, 20c, 20d). At least one is accessible both in a parallel and in a serial fashion. A functional unit (30) therein is coupled to two or more of the registers and comprises a chain of functional unit segments (31, 31′) that each comprise an AND gate (33) and a 1-bit full adder (32) receiving an output of the AND-gate. An output selection facility (50) provides an output signal of the configurable logic cell selected from two or more input signals. At least one of the input signals is provided by one of the multi-bit registers, and another by the functional unit.
摘要翻译：可配置逻辑器件包括多个可配置逻辑单元（2）。可配置逻辑单元包括多个多位寄存器（20a，20b，20c，20d）。至少一个可以并行和串行的方式访问。其中的功能单元（30）耦合到两个或更多个寄存器，并且包括一系列功能单元段（31,31'），每个链包括与门（33）和1位全加器（32），其接收 AND门的输出。输出选择装置（50）提供从两个或更多个输入信号中选择的可配置逻辑单元的输出信号。至少一个输入信号由多位寄存器之一提供，另一个由功能单元提供。

10. 发明申请

US20090267670A1 CIRCUIT WITH PARALLEL FUNCTIONAL CIRCUITS WITH MULTI-PHASE CONTROL INPUTS 有权
标题翻译：具有多相控制输入的并行功能电路的电路
公开(公告)号：US20090267670A1
公开(公告)日：2009-10-29
申请号：US12518696
申请日：2007-12-10
申请人： Paul Wielage , Martinus T. Bennebroek
发明人： Paul Wielage , Martinus T. Bennebroek
IPC分类号： H03K3/00 , G11C19/00
CPC分类号： G11C19/287 , G06F9/3869
摘要： A circuit has a plurality of functional circuits (100a-f), each with multiphase control inputs. A control circuit drives the inputs for each phase in parallel. The control circuit (120a-c) comprises a chain of one-shot circuits (120a-c), each comprising a bi-stable circuit (121). The bi-stable circuit (121) of a first one-shot circuit in the chain has a set input coupled to the basic control signal input (126), the bi-stable circuits (121) of a remaining or each remaining one-shot circuit (120a-c) in the chain have a set input output of its predecessor in the chain. Each bi-stable circuit (121) has an output coupled to a respective one of the multiphase control outputs (14a-c) and a reset input coupled to the respective one of the multiphase control outputs (14a-c). Loading of the multiphase control outputs (14a-c) by the functional circuits results in a delay of the reset. Thus the pulse durations of the one shot circuits are adapted to the number of functional circuits to ensure sufficient signal development.
摘要翻译：电路具有多个功能电路（100a-f），每个具有多相控制输入。控制电路并联驱动每相的输入。控制电路（120a-c）包括一个单触发电路链（120a-c），每条链包括双稳电路（121）。链中的第一单触发电路的双稳态电路（121）具有耦合到基本控制信号输入（126）的设置输入，剩余或每个剩余单次触发的双稳态电路（121）链路中的电路（120a-c）具有其前身在链中的设定输入输出。每个双稳态电路（121）具有耦合到多相控制输出（14a-c）中的相应一个的输出和耦合到多相控制输出（14a-c）中的相应一个的复位输入。通过功能电路加载多相控制输出（14a-c）会导致复位延迟。因此，单触发电路的脉冲持续时间适应于功能电路的数量，以确保足够的信号发展。

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