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1. 发明授权

US08809988B2 Low leakage and/or low turn-on voltage Schottky diode 有权
标题翻译：低泄漏和/或低导通电压肖特基二极管
公开(公告)号：US08809988B2
公开(公告)日：2014-08-19
申请号：US13061756
申请日：2009-09-03
申请人： Ji-Hyoung Yoo , Martin E. Garnett
发明人： Ji-Hyoung Yoo , Martin E. Garnett
IPC分类号： H01L29/40
CPC分类号： H01L29/872 , H01L21/26513 , H01L29/06 , H01L29/66143
摘要： A Schottky diode and a method of manufacturing the Schottky diode are disclosed. The Schottky diode has an N-well or N-epitaxial layer with a first region, a second region substantially adjacent to an electron doped buried layer that has a donor electron concentration greater than that of the first region, and a third region substantially adjacent to the anode that has a donor electron concentration that is less than that of the first region. The second region may be doped with implanted phosphorus and the third region may be doped with implanted boron.
摘要翻译：公开了肖特基二极管和制造肖特基二极管的方法。肖特基二极管具有N阱或N外延层，其具有第一区域，与电子掺杂掩埋层基本相邻的第二区域，其施主电子浓度大于第一区域的施主电子浓度，第三区域基本上邻近于所述阳极的供体电子浓度小于所述第一区域的供体电子浓度。第二区域可以掺杂有注入的磷，并且第三区域可以掺杂注入的硼。

2. 发明授权

US08598637B2 High voltage junction field effect transistor with spiral field plate 有权
标题翻译：具有螺旋场板的高压结型场效应晶体管
公开(公告)号：US08598637B2
公开(公告)日：2013-12-03
申请号：US12562328
申请日：2009-09-18
申请人： Michael R. Hsing , Martin E. Garnett , Ognjen Milic
发明人： Michael R. Hsing , Martin E. Garnett , Ognjen Milic
IPC分类号： H01L29/66
CPC分类号： H01L29/405 , H01L29/0692 , H01L29/808
摘要： In one embodiment, a junction field effect transistor having a substrate, wherein formed on the substrate is a graded n-doped region having a high doping concentration in an inner region and a low doping concentration in an outer region, with a p-doped buried region adjacent to the graded n-doped region near the outer region, and a spiral resistor connected to the graded n-doped region at its inner region and at its outer region. An ohmic contact at the inner region provides the drain, an ohmic contact at the outer region provides the source, and an ohmic contact at the substrate provides the gate.
摘要翻译：在一个实施例中，具有衬底的结场效应晶体管，其中形成在衬底上的是在内部区域具有高掺杂浓度并且在外部区域具有低掺杂浓度的渐变n掺杂区域，其中p掺杂埋入与在外部区域附近的渐变n掺杂区域相邻的区域，以及在其内部区域和其外部区域处连接到渐变n掺杂区域的螺旋电阻器。在内部区域处的欧姆接触提供漏极，在外部区域处的欧姆接触提供源极，并且在衬底处的欧姆接触提供栅极。

3. 发明授权

US07273761B2 Box-in-box field-to-field alignment structure 有权
标题翻译：箱内即场对齐结构
公开(公告)号：US07273761B2
公开(公告)日：2007-09-25
申请号：US10959551
申请日：2004-10-05
申请人： Robert W. Rumsey , Martin E. Garnett
发明人： Robert W. Rumsey , Martin E. Garnett
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： G03F7/70633 , G01B11/26 , G03F7/70616 , G03F9/7076 , Y10S438/975
摘要： A lithographic pattern includes a first scribe along an edge of a die region, and a second scribe along an opposing edge of the die region. The first scribe includes at least a first translucent box and a second translucent box. The second scribe includes at least a first opaque box and a second opaque box defined respectively by a first translucent frame and a second translucent frame. When the lithographic pattern is stepped between fields on a wafer, the first translucent box is placed at least partially within the first opaque box, and the second translucent box is placed at least partially within the second opaque box. If a continuous ring is formed from a pair of a translucent box and an opaque box, the fields are aligned at least within an amount equal to the difference between the dimensions of that translucent box and that opaque box divided by 2.
摘要翻译：平版印刷图案包括沿着模具区域的边缘的第一刻痕，以及沿着模具区域的相对边缘的第二划片。第一划痕至少包括第一半透明盒和第二透明盒。第二划片包括分别由第一半透明框架和第二半透明框架限定的至少第一不透明盒和第二不透明盒。当平版印刷图案在晶片上的场之间步进时，第一半透明盒至少部分地放置在第一不透明盒中，并且第二透明盒至少部分地放置在第二不透明盒内。如果从一对半透明盒和不透明盒形成连续的环，则这些场至少等于该半透明盒的尺寸和该不透明盒除以2的差的量。

4. 发明申请

US20110156199A1 LOW LEAKAGE AND/OR LOW TURN-ON VOLTAGE SCHOTTKY DIODE 有权
标题翻译：低漏电和/或低导通电压肖特基二极管
公开(公告)号：US20110156199A1
公开(公告)日：2011-06-30
申请号：US13061756
申请日：2009-09-03
申请人： Ji-Hyoung Yoo , Martin E. Garnett
发明人： Ji-Hyoung Yoo , Martin E. Garnett
IPC分类号： H01L29/872 , H01L21/329
CPC分类号： H01L29/872 , H01L21/26513 , H01L29/06 , H01L29/66143
摘要： A Schottky diode and a method of manufacturing the Schottky diode are disclosed. The Schottky diode has an N-well or N-epitaxial layer with a first region, a second region substantially adjacent to an electron doped buried layer that has a donor electron concentration greater than that of the first region, and a third region substantially adjacent to the anode that has a donor electron concentration that is less than that of the first region. The second region may be doped with implanted phosphorus and the third region may be doped with implanted boron.
摘要翻译：公开了肖特基二极管和制造肖特基二极管的方法。肖特基二极管具有N阱或N外延层，其具有第一区域，与电子掺杂掩埋层基本相邻的第二区域，其施主电子浓度大于第一区域的施主电子浓度;以及第三区域，所述阳极的供体电子浓度小于所述第一区域的供体电子浓度。第二区域可以掺杂有注入的磷，并且第三区域可以掺杂注入的硼。

5. 发明申请

US20110068410A1 SILICON DIE FLOORPLAN WITH APPLICATION TO HIGH-VOLTAGE FIELD EFFECT TRANSISTORS 审中-公开
标题翻译：应用于高压场效应晶体管的硅胶板
公开(公告)号：US20110068410A1
公开(公告)日：2011-03-24
申请号：US12750248
申请日：2010-03-30
申请人： Martin E. Garnett , Michael R. Hsing
发明人： Martin E. Garnett , Michael R. Hsing
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L27/0207 , H01L27/088 , H01L27/098 , H01L29/0692 , H01L29/405 , H01L29/808
摘要： A floorplan for a die having three high-voltage transistors for power applications is described. The three high-voltage transistors are specifically placed in relation to each other to optimize operation.
摘要翻译：描述了具有用于功率应用的三个高压晶体管的管芯的平面图。三个高压晶体管彼此相对放置，以优化操作。

6. 发明申请

US20110068377A1 HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR WITH SPIRAL FIELD PLATE 有权
标题翻译：具有螺旋场板的高电压场效应晶体管
公开(公告)号：US20110068377A1
公开(公告)日：2011-03-24
申请号：US12562328
申请日：2009-09-18
申请人： Michael R. Hsing , Martin E. Garnett , Ognjen Milic
发明人： Michael R. Hsing , Martin E. Garnett , Ognjen Milic
IPC分类号： H01L27/06
CPC分类号： H01L29/405 , H01L29/0692 , H01L29/808
摘要： In one embodiment, a junction field effect transistor having a substrate, wherein formed on the substrate is a graded n-doped region having a high doping concentration in an inner region and a low doping concentration in an outer region, with a p-doped buried region adjacent to the graded n-doped region near the outer region, and a spiral resistor connected to the graded n-doped region at its inner region and at its outer region. An ohmic contact at the inner region provides the drain, an ohmic contact at the outer region provides the source, and an ohmic contact at the substrate provides the gate.
摘要翻译：在一个实施例中，具有衬底的结场效应晶体管，其中形成在衬底上的是在内部区域具有高掺杂浓度并且在外部区域具有低掺杂浓度的渐变n掺杂区域，其中p掺杂埋入与在外部区域附近的渐变n掺杂区域相邻的区域，以及在其内部区域和其外部区域处连接到渐变n掺杂区域的螺旋电阻器。在内部区域处的欧姆接触提供漏极，在外部区域处的欧姆接触提供源极，并且在衬底处的欧姆接触提供栅极。

7. 发明授权

US06815128B2 Box-in-box field-to-field alignment structure 有权
标题翻译：箱内即场对齐结构
公开(公告)号：US06815128B2
公开(公告)日：2004-11-09
申请号：US10114701
申请日：2002-04-01
申请人： Robert W. Rumsey , Martin E. Garnett
发明人： Robert W. Rumsey , Martin E. Garnett
IPC分类号： G03F900
CPC分类号： G03F7/70633 , G01B11/26 , G03F7/70616 , G03F9/7076 , Y10S438/975
摘要： A lithographic pattern includes a first scribe along an edge of a die region, and a second scribe along an opposing edge of the die region. The first scribe includes at least a first translucent box and a second translucent box. The second scribe includes at least a first opaque box and a second opaque box defined respectively by a first translucent frame and a second translucent frame. When the lithographic pattern is stepped between fields on a wafer, the first translucent box is placed at least partially within the first opaque box, and the second translucent box is placed at least partially within the second opaque box. If a continuous ring is formed from a pair of a translucent box and an opaque box, the fields are aligned at least within an amount equal to the difference between the dimensions of that translucent box and that opaque box divided by 2.
摘要翻译：平版印刷图案包括沿着模具区域的边缘的第一刻痕，以及沿着模具区域的相对边缘的第二划片。第一划痕至少包括第一半透明盒和第二透明盒。第二划片包括分别由第一半透明框架和第二半透明框架限定的至少第一不透明盒和第二不透明盒。当平版印刷图案在晶片上的场之间步进时，第一半透明盒至少部分地放置在第一不透明盒中，并且第二透明盒至少部分地放置在第二不透明盒内。如果从一对半透明盒和不透明盒形成连续的环，则这些场至少等于该半透明盒的尺寸和该不透明盒除以2的差的量。

8. 发明授权

US06163140A Start-up circuit for voltage regulators 有权
标题翻译：稳压器启动电路
公开(公告)号：US06163140A
公开(公告)日：2000-12-19
申请号：US495488
申请日：2000-02-01
申请人： Martin E. Garnett , Andrew M. Cowell , Steve I. Chaney
发明人： Martin E. Garnett , Andrew M. Cowell , Steve I. Chaney
IPC分类号： G05F1/46 , G05F1/56 , H02M1/00 , H02M1/36 , G05F1/10 , H02J3/12
CPC分类号： H02M1/36 , G05F1/468 , G05F1/56 , Y10S323/901
摘要： A start-up circuit for voltage regulators includes a depletion mode field effect transistor (FET) having a drain electrically coupled to an input voltage, a source electrically coupled to the voltage regulator power supply input terminal and to a voltage corresponding to an output voltage of the voltage regulator, a body at a fixed voltage, and a gate electrically coupled to the output of a comparator. At start-up, the voltage regulator is powered through the FET. The drain current is self-limiting, preventing the source of the FET from rising to the level of the input voltage. When the rising output voltage of the regulator reaches a level that can operate the regulator control circuit, the comparator grounds the gate of the FET to turn off the FET, and the voltage regulator operates off of its own output. Virtually no power is dissipated in the FET during steady-state operation of the regulator.
摘要翻译：用于稳压器的启动电路包括具有电耦合到输入电压的漏极的耗尽型场效应晶体管（FET），电耦合到电压调节器电源输入端的源和与电压调节器电源输入端的输出电压相对应的电压电压调节器，固定电压的主体以及电耦合到比较器的输出的栅极。启动时，电压调节器通过FET供电。漏极电流是自限制的，防止FET的源极上升到输入电压的电平。当稳压器的上升输出电压达到能够调节稳压器电路的电平时，比较器将FET的栅极接通，关闭FET，并且电压调节器自身输出。在调节器的稳态运行期间，FET几乎没有耗散功率。

9. 发明授权

US5753391A Method of forming a resistor having a serpentine pattern through multiple use of an alignment keyed mask 失效
标题翻译：通过多次使用对准键控掩模形成具有蛇形图案的电阻器的方法
公开(公告)号：US5753391A
公开(公告)日：1998-05-19
申请号：US535000
申请日：1995-09-27
申请人： Marshall D. Stone , Martin E. Garnett , Michael J. Mottola , Hiu F. Ip
发明人： Marshall D. Stone , Martin E. Garnett , Michael J. Mottola , Hiu F. Ip
IPC分类号： G03F9/00 , H01C7/22 , H01C17/24
CPC分类号： G03F9/00 , H01C17/2416 , H01C7/22 , Y10S148/102 , Y10T29/49156
摘要： Each die containing a resistive element which is to be trimmed has associated therewith a plurality of alignment targets. A cut mask having a trim pattern and an alignment key formed thereon is employed in a masking and etching step to trim the resistive element to a desired resistance. The number of links cut in the resistive element, and thus the final resistance thereof, depends on the particular positioning of the cut mask with respect to the die as determined by which of the alignment targets is aligned with the alignment key. For instance, aligning the alignment key with a first alignment target would result in cutting one link in the resistive element so as to achieve a first resistance value, while re-aligning the cut mask such that the alignment key aligns with another of the alignment targets would result in cutting two links in the resistive element so as to achieve a second resistance value. Since the trim of resistive elements may be adjusted to any one of many possible resistance values by simply changing the alignment of the cut mask with respect to the die, the need to have a separate cut mask for each of the possible trimmed resistance values is eliminated, thereby reducing costs.
摘要翻译：包含要修剪的电阻元件的每个管芯都具有多个对准靶。在掩模和蚀刻步骤中采用具有修剪图案和形成在其上的对准键的切割掩模，以将电阻元件修剪到期望的电阻。在电阻元件中切割的连接数量以及其最终电阻取决于切割掩模相对于管芯的特定定位，由哪个对准靶与对准键对准确定。例如，将对准键与第一对准目标对准将导致切割电阻元件中的一个连杆，以便实现第一电阻值，同时重新对准切割掩模，使得对准键与另一个对准目标对准将导致在电阻元件中切割两个连接以实现第二电阻值。由于可以通过简单地改变切割掩模相对于管芯的对准来将电阻元件的修剪调节到许多可能的电阻值中的任何一个，因此消除了对每个可能的修剪电阻值具有单独的切割掩模的需要，从而降低成本。

10. 发明授权

US5556796A Self-alignment technique for forming junction isolation and wells 失效
标题翻译：用于形成结隔离和井的自对准技术
公开(公告)号：US5556796A
公开(公告)日：1996-09-17
申请号：US428929
申请日：1995-04-25
申请人： Martin E. Garnett , Michael R. Hsing
发明人： Martin E. Garnett , Michael R. Hsing
IPC分类号： H01L27/06 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L21/265
CPC分类号： H01L21/8249 , Y10S148/009
摘要： A method in accordance with one embodiment of the present invention may be used to self-align isolation regions, sinkers, and wells. In this improved method, P+ isolation regions, N+ sinkers, and P-wells are defined using the same masking step used to define the N-wells. The use of a single masking step to initially define the P+ isolation regions, N+ sinkers, N-wells, and P-wells results in the self-alignment of these regions. Several critical mask alignments are thereby eliminated, thus avoiding/simplifying fabrication steps, conserving die area, and allowing increased component density.
摘要翻译：根据本发明的一个实施例的方法可以用于自对准隔离区域，沉降片和井。在这种改进的方法中，使用用于定义N阱的相同掩蔽步骤来定义P +隔离区域，N +沉降物和P阱。使用单个掩蔽步骤来初始地定义P +隔离区，N +沉降片，N阱和P阱导致这些区域的自对准。由此消除了几个关键的掩模对准，从而避免/简化制造步骤，节省管芯面积并允许增加的部件密度。

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