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1. 发明授权

US08572525B2 Partition response surface modeling 有权
标题翻译：分区响应面建模
公开(公告)号：US08572525B2
公开(公告)日：2013-10-29
申请号：US12861777
申请日：2010-08-23
申请人： Marko P Chew , Yue Yang , Toshikazu Endo
发明人： Marko P Chew , Yue Yang , Toshikazu Endo
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36 , G03F1/68
摘要： A group of models are developed to predict printed contour deviations relative to the corresponding layout edges for different classes of layout topologies. A plurality of calibration layouts with topologies belonging to a class of layout topologies are used to generate a model for the class of layout topologies. A standard least square regression is modified for model creation. The model error may be monitored dynamically.
摘要翻译：开发了一组模型来预测相对于不同类型布局拓扑的相应布局边缘的印刷轮廓偏差。使用具有属于一类布局拓扑的拓扑的多个校准布局来生成布局拓扑类的模型。修改模型创建的标准最小二乘回归。可以动态地监视模型错误。

2. 发明授权

US08099685B2 Model based microdevice design layout correction 有权
标题翻译：基于模型的微型设计布局校正
公开(公告)号：US08099685B2
公开(公告)日：2012-01-17
申请号：US12184089
申请日：2008-07-31
申请人： Marko P Chew , Yue Yang , Juan Andres Torres Robles
发明人： Marko P Chew , Yue Yang , Juan Andres Torres Robles
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Shapes neighboring a potential manufacturing fault within a microdevice design layout are identified. Models are employed to determine the affect of the shapes upon the potential manufacturing fault. Possible adjustments to the shapes are modeled. The possible adjustments facilitating resolution of the potential manufacturing fault.
摘要翻译：识别出与微设计设计布局相邻的潜在制造故障的形状。模型用于确定形状对潜在制造故障的影响。可以对形状进行可能的调整。可能的调整有助于解决潜在的制造故障。

3. 发明授权

US07886262B2 System and method of maximizing integrated circuit manufacturing yield with fabrication process simulation driven layout optimization 有权
标题翻译：通过制造过程仿真驱动布局优化最大化集成电路制造产量的系统和方法
公开(公告)号：US07886262B2
公开(公告)日：2011-02-08
申请号：US11888597
申请日：2007-08-01
申请人： Marko P. Chew , Yue Yang
发明人： Marko P. Chew , Yue Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A system and a method of maximizing the manufacturing yield of integrated circuit (“IC”) design using IC fabrication process simulation driven layout optimization is described. An IC design layout is automatically modified through formulation of a layout optimization problem utilizing the results of layout fabrication process compliance analysis tools. The modification of layout is performed adaptively and iteratively to make an IC layout less susceptible to yield issues while maintaining design rule correctness and minimal circuit performance impact.
摘要翻译：描述了使用IC制造过程模拟驱动布局优化来最大化集成电路（“IC”）设计的制造产量的系统和方法。利用布局制作流程合规性分析工具的结果，通过制定布局优化问题自动修改IC设计布局。布局的修改被自适应地和迭代地执行，使得IC布局不容易产生问题，同时保持设计规则的正确性和最小的电路性能影响。

4. 发明授权

US07761819B2 System and method of modification of integrated circuit mask layout 失效
标题翻译：集成电路面板布局修改的系统和方法
公开(公告)号：US07761819B2
公开(公告)日：2010-07-20
申请号：US11824749
申请日：2007-07-02
申请人： Yue Yang , Marko P. Chew
发明人： Yue Yang , Marko P. Chew
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Integrated circuit mask layouts are modified for the purpose of migration to abide a new set of design rules, or for the purpose of optimization for timing, power, signal integrity and manufacturability, among other purposes. The modified layout is required to satisfy a set of constraints generated from design rules, electrical specifications, user specifications among other requirements. The present invention provides a system and a method of representing constraint sets, each of which consists of two or more sets of constraints that are mutually exclusive to each other. In the preferred embodiment, one method of formulation is presented, and a method of solving the layout modification problem under the constraint sets is presented.
摘要翻译：修改了集成电路掩模布局，以便迁移以遵守新的一组设计规则，或为了优化时序，功率，信号完整性和可制造性等目的。需要修改的布局来满足从设计规则，电气规格，用户规格以及其他要求产生的一组约束。本发明提供了一种表示约束集的系统和方法，每个约束集由彼此相互排斥的两组或多组约束组成。在优选实施例中，提出了一种制定方法，并且提出了一种解决约束集下的布局修改问题的方法。

5. 发明申请

US20100023916A1 Model Based Hint Generation For Lithographic Friendly Design 审中-公开
标题翻译：用于光刻友好设计的基于模型的提示生成
公开(公告)号：US20100023916A1
公开(公告)日：2010-01-28
申请号：US12416077
申请日：2009-03-31
申请人： Marko P. Chew , Yue Yang , Juan Andres Torres Robles
发明人： Marko P. Chew , Yue Yang , Juan Andres Torres Robles
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： In various implementations of the invention, a model of an optical proximity correction process is employed to determine potential adjustments to a layout design for a mask that might resolve potential errors an image resulting from application of the mask in an optical lithographic process. In various implementations of the invention, corrected mask shapes, such as for example optical proximity corrected mask shapes, and associated printed image contours are generated through use of a model. Subsequently, the associated printed image contour and a desired printed image contour may be used to determine various edge segment adjustments to the corrected mask shapes that would realize the desired printed image contour. In various implementations of the present invention, the model for generation of the corrected mask shapes and the associated printed image contour is a square kernel model. With various implementations of the invention, the kernel represents a grey scale map wherein each pixel of the map is generated based on the desired displacement relative to the displacement to be modeled. For example by application of linear regression techniques. As a result, printed image contours and corrected mask shapes may be generated based upon an input layout design, wherein potential adjustments to the mask may be determined based upon a desired printed image contour.
摘要翻译：在本发明的各种实施方案中，采用光学邻近校正处理的模型来确定对于掩模的布局设计的潜在调整，该掩模可以解决由于在光学平版印刷工艺中应用掩模而产生的图像的潜在错误。在本发明的各种实现中，通过使用模型来生成校正的掩模形状，例如光学邻近校正的掩模形状和相关的打印的图像轮廓。随后，可以使用相关联的打印图像轮廓和期望的打印图像轮廓来确定将实现期望的打印图像轮廓的校正的蒙版形状的各种边缘段调整。在本发明的各种实现中，用于生成校正的掩模形状的模型和相关联的打印图像轮廓是平方内核模型。通过本发明的各种实现，内核表示灰度图，其中基于相对于要建模的位移的期望位移来生成地图的每个像素。例如通过应用线性回归技术。结果，可以基于输入布局设计来生成打印图像轮廓和校正的掩模形状，其中可以基于期望的打印图像轮廓来确定对掩模的潜在调整。

6. 发明授权

US07761824B2 System and method to generate an IC layout using simplified manufacturing rule 失效
标题翻译：使用简化制造规则生成IC布局的系统和方法
公开(公告)号：US07761824B2
公开(公告)日：2010-07-20
申请号：US11824759
申请日：2007-07-02
申请人： Marko P. Chew , Yue Yang
发明人： Marko P. Chew , Yue Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Some embodiments of the invention provide a system and method where a physical design (“PD”) process can use simplified manufacturing rules to generate an integrated circuit (“IC”) layout. A layout optimization process transforms the PD generated layout to become more manufacturing rule compliant layout using a full set of manufacturing rules. The invention increases the probability of the PD process successfully generates an IC layout since the PD is not burdened with having to consider the full complexity of the manufacturing rules.
摘要翻译：本发明的一些实施例提供一种系统和方法，其中物理设计（“PD”）过程可以使用简化的制造规则来生成集成电路（“IC”）布局。布局优化过程使用完整的制造规则将PD生成的布局转换为更符合制造规则的布局。本发明增加了PD过程成功地生成IC布局的概率，因为PD不必考虑制造规则的完全复杂性。

7. 发明授权

US07739627B2 System and method of maximizing integrated circuit manufacturing yield with context-dependent yield cells 失效
标题翻译：利用上下文依赖性产量单元最大化集成电路制造产量的系统和方法
公开(公告)号：US07739627B2
公开(公告)日：2010-06-15
申请号：US11824758
申请日：2007-07-02
申请人： Marko P. Chew , Yue Yang
发明人： Marko P. Chew , Yue Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A system and a method of creating context dependent yield variants of integrated circuit (“IC”) design components and using these variants during a physical design of an IC block to maximize manufacturing yield are described. A plurality of variants of each design component is generated and characterized with manufacturing yield as a function of neighboring context (“context”) that includes, but is not limited to, neighboring design components and other layout objects and shapes. The present invention describes a system and method where a physical design process, in addition to satisfying design and performance requirements such as, but not limited to, power, timing, signal integrity and minimal layout area, selects context dependent yield variants to maximize manufacturing yield.
摘要翻译：描述了在IC块的物理设计期间创建集成电路（“IC”）设计组件的上下文相关产量变体并且使用这些变体以最大化制造产量的系统和方法。每个设计组件的多个变体被生成并表征为具有作为相邻上下文（“上下文”）的函数的制造成品率，其包括但不限于相邻设计组件和其他布局对象和形状。本发明描述了一种系统和方法，其中除了满足设计和性能要求（例如但不限于功率，定时，信号完整性和最小布局面积）外，物理设计过程选择上下文相关的屈服变型以最大化制造产量。

8. 发明申请

US20090113359A1 Model Based Microdevice Design Layout Correction 有权
标题翻译：基于模型的微装置设计布局校正
公开(公告)号：US20090113359A1
公开(公告)日：2009-04-30
申请号：US12184089
申请日：2008-07-31
申请人： Marko P. Chew , Yue Yang , Juan Andres Torres Robles
发明人： Marko P. Chew , Yue Yang , Juan Andres Torres Robles
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Shapes neighboring a potential manufacturing fault within a microdevice design layout are identified. Models are employed to determine the affect of the shapes upon the potential manufacturing fault. Possible adjustments to the shapes are modeled. The possible adjustments facilitating resolution of the potential manufacturing fault.
摘要翻译：识别出与微设计设计布局相邻的潜在制造故障的形状。模型用于确定形状对潜在制造故障的影响。可以对形状进行可能的调整。可能的调整有助于解决潜在的制造故障。

9. 发明申请

US20080046846A1 System and method of maximizing integrated circuit manufacturing yield with fabrication process simulation driven layout optimization 有权
标题翻译：通过制造过程仿真驱动布局优化最大化集成电路制造产量的系统和方法
公开(公告)号：US20080046846A1
公开(公告)日：2008-02-21
申请号：US11888597
申请日：2007-08-01
申请人： Marko P. Chew , Yue Yang
发明人： Marko P. Chew , Yue Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A system and a method of maximizing the manufacturing yield of integrated circuit (“IC”) design using IC fabrication process simulation driven layout optimization is described. An IC design layout is automatically modified through formulation of a layout optimization problem utilizing the results of layout fabrication process compliance analysis tools. The modification of layout is performed adaptively and iteratively to make an IC layout less susceptible to yield issues while maintaining design rule correctness and minimal circuit performance impact.
摘要翻译：描述了使用IC制造过程模拟驱动布局优化来最大化集成电路（“IC”）设计的制造产量的系统和方法。利用布局制作流程合规性分析工具的结果，通过制定布局优化问题自动修改IC设计布局。布局的修改被自适应地和迭代地执行，使得IC布局不容易产生问题，同时保持设计规则的正确性和最小的电路性能影响。

10. 发明申请

US20080022235A1 System and method of maximizing integrated circuit manufacturing yield with context-dependent yield cells 失效
标题翻译：利用上下文依赖性产量单元最大化集成电路制造产量的系统和方法
公开(公告)号：US20080022235A1
公开(公告)日：2008-01-24
申请号：US11824758
申请日：2007-07-02
申请人： Marko P. Chew , Yue Yang
发明人： Marko P. Chew , Yue Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A system and a method of creating context dependent yield variants of integrated circuit (“IC”) design components and using these variants during a physical design of an IC block to maximize manufacturing yield are described. A plurality of variants of each design component is generated and characterized with manufacturing yield as a function of neighboring context (“context”) that includes, but is not limited to, neighboring design components and other layout objects and shapes. The present invention describes a system and method where a physical design process, in addition to satisfying design and performance requirements such as, but not limited to, power, timing, signal integrity and minimal layout area, selects context dependent yield variants to maximize manufacturing yield.
摘要翻译：描述了在IC块的物理设计期间创建集成电路（“IC”）设计组件的上下文相关产量变体并且使用这些变体以最大化制造产量的系统和方法。每个设计组件的多个变体被生成并表征为具有作为相邻上下文（“上下文”）的函数的制造成品率，其包括但不限于相邻设计组件和其他布局对象和形状。本发明描述了一种系统和方法，其中除了满足设计和性能要求（例如但不限于功率，定时，信号完整性和最小布局面积）外，物理设计过程选择上下文相关的屈服变型以最大化制造产量。

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