专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08352657B2 Digital device interconnect interface and system 有权
标题翻译：数字设备互连接口和系统
公开(公告)号：US08352657B2
公开(公告)日：2013-01-08
申请号：US13246365
申请日：2011-09-27
申请人： Mark R. Bohm
发明人： Mark R. Bohm
IPC分类号： G06F13/42
CPC分类号： G06F13/4291 , G06F1/3203 , G06F1/3253 , G06F2213/0042 , Y02D10/151
摘要： A simple data transfer mechanism may be combined with static state bus signaling to replace a USB with a digital serial interconnect bus (DSIB). This may eliminate various pull-up/pull-down resistors required in USB, and enable the DSIB to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The DSIB may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The DSIB may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.
摘要翻译：简单的数据传输机制可以与静态总线信号组合，以用数字串行互连总线（DSIB）代替USB。这可以消除USB中所需的各种上拉/下拉电阻，并且当总线处于空闲状态或数据传输状态时，使DSIB能够很少或没有泄漏电流工作。所有必需的功能可以仅使用两个信号引脚来实现。 DSIB还可以为不需要PLL的高速USB启用硅解决方案，因为时钟可能由传输源提供，因此可能不需要从串行数据流中恢复。 DSIB可以通过使设计人员能够移除模拟PHY并用串行数字I / O传输机制替代它，同时保留IP的USB定时器以及其他协议特定功能，为USB芯片提供了一个简单的重用机制。

2. 发明授权

US07631111B2 System method for rapidly charging USB device's battery wherein USB device requests charging the battery at a higher power level 有权
标题翻译：用于快速充电USB设备电池的系统方法，其中USB设备请求以更高的功率电平对电池充电
公开(公告)号：US07631111B2
公开(公告)日：2009-12-08
申请号：US11465189
申请日：2006-08-17
申请人： Morgan H. Monks , Mark R. Bohm
发明人： Morgan H. Monks , Mark R. Bohm
IPC分类号： G06F3/00 , G06F1/00
CPC分类号： H04L12/10 , H02J7/0036
摘要： System and method for enumerating and/or enumerating a device. The device may be a USB portable device which adheres to a first standard, e.g., the USB specification, and may engage in enumeration with respect to a USB hub/USB host device. Where a battery included in the device is sufficiently low, the device may engage in low power enumeration, e.g., to begin charging the device using enumerated power. Low power enumeration may allow the device to enumerate even when the device is incapable of powering on. Additionally, or alternatively, the device may determine whether the hub/host device is capable of providing high power charging. If it is, the device may begin charging the battery of the device using power provided by the hub/host device at a high power level.
摘要翻译：用于枚举和/或枚举设备的系统和方法。该设备可以是遵守第一标准（例如USB规范）的USB便携式设备，并且可以参照关于USB集线器/ USB主机设备的枚举。在设备中包括的电池足够低的情况下，该设备可以从事低功率枚举，例如开始使用枚举功率对设备充电。低功耗枚举可能允许设备枚举，即使设备无法启动。另外或替代地，设备可以确定集线器/主设备是否能够提供高功率充电。如果是，则设备可以使用由集线器/主机设备提供的功率以高功率电平开始对设备的电池充电。

3. 发明授权

US07624202B2 System and method for enumerating a USB device using low power 有权
标题翻译：使用低功耗枚举USB设备的系统和方法
公开(公告)号：US07624202B2
公开(公告)日：2009-11-24
申请号：US11465195
申请日：2006-08-17
申请人： Morgan H. Monks , Mark R. Bohm
发明人： Morgan H. Monks , Mark R. Bohm
IPC分类号： G06F3/00 , G06F1/00
CPC分类号： G06F1/266
摘要： System and method for enumerating and/or enumerating a device. The device may be a USB portable device which adheres to a first standard, e.g., the USB specification, and may engage in enumeration with respect to a USB hub/USB host device. Where a battery included in the device is sufficiently low, the device may engage in low power enumeration, e.g., to begin charging the device using enumerated power. Low power enumeration may allow the device to enumerate even when the device is incapable of powering on. Additionally, or alternatively, the device may determine whether the hub/host device is capable of providing high power charging. If it is, the device may begin charging the battery of the device using power provided by the hub/host device at a high power level.
摘要翻译：用于枚举和/或枚举设备的系统和方法。该设备可以是遵守第一标准（例如USB规范）的USB便携式设备，并且可以参照关于USB集线器/ USB主机设备的枚举。在设备中包括的电池足够低的情况下，该设备可以从事低功率枚举，例如开始使用枚举功率对设备充电。低功耗枚举可能允许设备枚举，即使设备无法启动。另外或替代地，设备可以确定集线器/主设备是否能够提供高功率充电。如果是，则设备可以使用由集线器/主机设备提供的功率以高功率电平开始对设备的电池充电。

4. 发明申请

US20080191756A1 AUTOMATIC SYSTEM CLOCK DETECTION SYSTEM 有权
标题翻译：自动系统时钟检测系统
公开(公告)号：US20080191756A1
公开(公告)日：2008-08-14
申请号：US11939670
申请日：2007-11-14
申请人： Shawn Shaojie Li , Akhlesh Nigam , Mark R. Bohm , Michael J. Pennell
发明人： Shawn Shaojie Li , Akhlesh Nigam , Mark R. Bohm , Michael J. Pennell
IPC分类号： H03L7/06 , H03L7/00
CPC分类号： H03L7/0995
摘要： An Automatic System Clock Detection System (ASCDS) may provide integrated circuits (ICs) with the capability to detect the frequency of an external crystal oscillator or clock source, and adjust the IC's internal PLL accordingly for proper IC operation. The frequency detection and PLL adjustment may be performed without any additional pins on the IC, and/or without requiring any additional external information. The ASCDS may be configured with an internal ring oscillator, which may be generated from standard logic elements, a watchdog counter, and an input clock counter. When the IC comes out of power on reset (POR), the ASCDS may compare the input clock counter with the watchdog counter, and determine the clock frequency of the input clock. It may then set the PLL parameters to ensure correct IC operation.
摘要翻译：自动系统时钟检测系统（ASCDS）可以提供具有检测外部晶体振荡器或时钟源的频率的集成电路（IC），并相应调整IC的内部PLL以进行适当的IC操作。可以在IC上没有任何额外的引脚进行频率检测和PLL调整，和/或不需要任何额外的外部信息。 ASCDS可以配置有内部环形振荡器，其可以由标准逻辑元件，看门狗计数器和输入时钟计数器产生。当IC掉电上电（POR）时，ASCDS可以将输入时钟计数器与看门狗计数器进行比较，并确定输入时钟的时钟频率。然后可以设置PLL参数以确保正确的IC操作。

5. 发明申请

US20080042616A1 System and Method for Rapidly Charging a USB Device 有权
标题翻译：快速充电USB设备的系统和方法
公开(公告)号：US20080042616A1
公开(公告)日：2008-02-21
申请号：US11465189
申请日：2006-08-17
申请人： Morgan H. Monks , Mark R. Bohm
发明人： Morgan H. Monks , Mark R. Bohm
IPC分类号： H02J7/00
CPC分类号： H04L12/10 , H02J7/0036
摘要： System and method for enumerating and/or enumerating a device. The device may be a USB portable device which adheres to a first standard, e.g., the USB specification, and may engage in enumeration with respect to a USB hub/USB host device. Where a battery included in the device is sufficiently low, the device may engage in low power enumeration, e.g., to begin charging the device using enumerated power. Low power enumeration may allow the device to enumerate even when the device is incapable of powering on. Additionally, or alternatively, the device may determine whether the hub/host device is capable of providing high power charging. If it is, the device may begin charging the battery of the device using power provided by the hub/host device at a high power level.
摘要翻译：用于枚举和/或枚举设备的系统和方法。该设备可以是遵守第一标准（例如USB规范）的USB便携式设备，并且可以参照关于USB集线器/ USB主机设备的枚举。在设备中包括的电池足够低的情况下，该设备可以从事低功率枚举，例如开始使用枚举功率对设备充电。低功耗枚举可能允许设备枚举，即使设备无法启动。另外或替代地，设备可以确定集线器/主设备是否能够提供高功率充电。如果是，则设备可以使用由集线器/主机设备提供的功率以高功率电平开始对设备的电池充电。

6. 发明申请

US20090106474A1 Multi-Host USB Device 有权
标题翻译：多主机USB设备
公开(公告)号：US20090106474A1
公开(公告)日：2009-04-23
申请号：US12340957
申请日：2008-12-22
申请人： Mark R. Bohm , Atish Ghosh
发明人： Mark R. Bohm , Atish Ghosh
IPC分类号： G06F13/36
CPC分类号： G06F13/385
摘要： A USB device may be simultaneously configured and accessed by two or more USB hosts. The USB device may include separate upstream ports and buffers for each host, and a multi-host capable device controller configured to respond to simultaneous USB requests received from more than one host. The USB device may maintain a dedicated address, configuration, and response information for each host. The USB device may include a shared USB function block, and a multi-host controller configured to establish concurrent respective USB connections between the shared USB function block and two or more USB hosts, to allow the two or more USB hosts to simultaneously configure the USB device for the shared USB function. The multi-host controller may be configured to receive and respond to simultaneous respective USB access requests for the shared USB function sent by the two or more USB hosts.
摘要翻译： USB设备可以由两个或多个USB主机同时配置和访问。 USB设备可以包括用于每个主机的单独的上行端口和缓冲器，以及被配置为响应从多于一个主机接收到的USB同步请求的多主机设备控制器。 USB设备可以维护每个主机的专用地址，配置和响应信息。 USB设备可以包括共享USB功能块，以及配置成在共享USB功能块和两个或更多个USB主机之间建立并发的相应USB连接的多主机控制器，以允许两个或多个USB主机同时配置USB 用于共享USB功能的设备。多主机控制器可以被配置为接收并响应由两个或更多个USB主机发送的共享USB功能的同时各自的USB访问请求。

7. 发明授权

US07480753B2 Switching upstream and downstream logic between ports in a universal serial bus hub 有权
标题翻译：在通用串行总线集线器的端口之间切换上游和下游逻辑
公开(公告)号：US07480753B2
公开(公告)日：2009-01-20
申请号：US11412431
申请日：2006-04-27
申请人： Mark R. Bohm , Donald L. Perkins , Carl J. Crawford
发明人： Mark R. Bohm , Donald L. Perkins , Carl J. Crawford
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F2213/0042
摘要： System and method for switching logic in a Universal Serial Bus hub. The USB hub may include upstream logic and downstream logic for sending and receiving information from a host controller and a USB device respectively. The USB hub may include a plurality of ports operable to couple to a plurality of devices, including a first port coupled to the upstream logic and a second port coupled to the downstream logic. The USB hub may also include switching logic operable to switch the upstream and the downstream logic with respect to the first port and the second port respectively. The switching logic may switch the upstream and downstream logic by decoupling the first port from the upstream logic, decoupling the second port from the downstream logic, and coupling the second port to the upstream logic. Additionally, the first port may be coupled to the downstream logic.
摘要翻译：用于在通用串行总线集线器中切换逻辑的系统和方法。 USB集线器可以包括用于分别从主机控制器和USB设备发送和接收信息的上游逻辑和下游逻辑。 USB集线器可以包括可操作以耦合到多个设备的多个端口，包括耦合到上游逻辑的第一端口和耦合到下游逻辑的第二端口。 USB集线器还可以包括可操作以分别相对于第一端口和第二端口切换上游和下游逻辑的交换逻辑。切换逻辑可以通过将第一端口与上游逻辑解耦来解耦上游和下游逻辑，将第二端口与下游逻辑解耦，并将第二端口耦合到上游逻辑。另外，第一端口可以耦合到下游逻辑。

8. 发明申请

US20070288671A1 LOW POWER AND LOW PIN COUNT BI-DIRECTIONAL DUAL DATA RATE DEVICE INTERCONNECT INTERFACE 有权
标题翻译：低功率和低引脚数双向数据速率设备互连接口
公开(公告)号：US20070288671A1
公开(公告)日：2007-12-13
申请号：US11428211
申请日：2006-06-30
申请人： Mark R. Bohm
发明人： Mark R. Bohm
IPC分类号： G06F13/42
CPC分类号： G06F13/4291 , G06F1/3203 , G06F1/3253 , G06F2213/0042 , Y02D10/151
摘要： A simple clock source synchronous DDR data transfer mechanism may be combined with static bus state signaling to replace a complex bus (e.g. USB) with an easy to implement digital serial interconnect bus. This may eliminate various pull-up/pull-down resistors required in USB, and enable the interconnect bus to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The interconnect bus may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The digital serial interconnect bus may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.
摘要翻译：简单的时钟源同步DDR数据传输机制可以与静态总线状态信令组合以用易于实现的数字串行互连总线来代替复杂总线（例如USB）。这可以消除USB中所需的各种上拉/下拉电阻，并且当总线处于空闲状态或数据传输状态时，使互连总线能够很少或没有泄漏电流工作。所有必需的功能可以仅使用两个信号引脚来实现。互连总线还可以为不需要PLL的高速USB启用硅解决方案，因为时钟可以由传输源提供，因此可能不需要从串行数据流中恢复。数字串行互连总线可以通过使设计人员能够移除模拟PHY并用串行数字I / O传输机制替代它，同时保留IP的USB定时器以及其他协议特定的功能，为USB芯片提供了一个简单的重用机制。

9. 发明申请

US20120137032A1 Digital Device Interconnect Interface and System 有权
标题翻译：数字设备互连接口和系统
公开(公告)号：US20120137032A1
公开(公告)日：2012-05-31
申请号：US13246365
申请日：2011-09-27
申请人： Mark R. Bohm
发明人： Mark R. Bohm
IPC分类号： G06F13/42
CPC分类号： G06F13/4291 , G06F1/3203 , G06F1/3253 , G06F2213/0042 , Y02D10/151
摘要： A simple data transfer mechanism may be combined with static state bus signaling to replace a USB with a digital serial interconnect bus (DSIB). This may eliminate various pull-up/pull-down resistors required in USB, and enable the DSIB to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The DSIB may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The DSIB may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.
摘要翻译：简单的数据传输机制可以与静态总线信号组合，以用数字串行互连总线（DSIB）代替USB。这可以消除USB中所需的各种上拉/下拉电阻，并且当总线处于空闲状态或数据传输状态时，使DSIB能够很少或没有泄漏电流工作。所有必需的功能可以仅使用两个信号引脚来实现。 DSIB还可以为不需要PLL的高速USB启用硅解决方案，因为时钟可能由传输源提供，因此可能不需要从串行数据流中恢复。 DSIB可以通过使设计人员能够移除模拟PHY并用串行数字I / O传输机制替代它，同时保留IP的USB定时器以及其他协议特定功能，为USB芯片提供了一个简单的重用机制。

10. 发明授权

US08055825B2 Digital device interconnect method 有权
标题翻译：数字设备互连方式
公开(公告)号：US08055825B2
公开(公告)日：2011-11-08
申请号：US12762823
申请日：2010-04-19
申请人： Mark R. Bohm
发明人： Mark R. Bohm
IPC分类号： G06F13/42
CPC分类号： G06F13/4291 , G06F1/3203 , G06F1/3253 , G06F2213/0042 , Y02D10/151
摘要： A simple clock source synchronous DDR data transfer mechanism may be combined with static bus state signaling to replace a complex bus (e.g. USB) with an easy to implement digital serial interconnect bus. This may eliminate various pull-up/pull-down resistors required in USB, and enable the interconnect bus to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The interconnect bus may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The digital serial interconnect bus may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.
摘要翻译：简单的时钟源同步DDR数据传输机制可以与静态总线状态信令组合以用易于实现的数字串行互连总线来代替复杂总线（例如USB）。这可以消除USB中所需的各种上拉/下拉电阻，并且当总线处于空闲状态或数据传输状态时，使互连总线能够很少或没有泄漏电流工作。所有必需的功能可以仅使用两个信号引脚来实现。互连总线还可以为不需要PLL的高速USB启用硅解决方案，因为时钟可以由传输源提供，因此可能不需要从串行数据流中恢复。数字串行互连总线可以通过使设计人员能够移除模拟PHY并用串行数字I / O传输机制替代它，同时保留IP的USB定时器以及其他协议特定的功能，为USB芯片提供了一个简单的重用机制。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式