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1. 发明授权

US07627462B2 Hardware simulation using a test scenario manager 有权
标题翻译：使用测试场景管理器进行硬件仿真
公开(公告)号：US07627462B2
公开(公告)日：2009-12-01
申请号：US09994023
申请日：2001-11-27
申请人： Andrew Mark Nightingale
发明人： Andrew Mark Nightingale
IPC分类号： G06F17/50
CPC分类号： G01R31/318357 , G06F17/5022
摘要： A hardware simulation and validation system is provided using a plurality of signal interface controllers to exchange stimulus and response signals with a hardware simulation. The action of the signal interface controllers is coordinated by a test scenario manager which exchanges test scenario controlling messages with the signal interface controllers. The test scenario controlling messages specify simulation actions to be performed and when those simulation actions are to be performed.
摘要翻译：使用多个信号接口控制器提供硬件仿真和验证系统以通过硬件模拟来交换激励和响应信号。信号接口控制器的动作由与信号接口控制器交换测试场景控制消息的测试场景管理器进行协调。测试场景控制消息指定要执行的模拟动作，以及何时将执行这些模拟动作。

2. 发明申请

US20050263317A1 INVERTED STRAIN RELIEF 有权
标题翻译：反应的应变救济
公开(公告)号：US20050263317A1
公开(公告)日：2005-12-01
申请号：US10856291
申请日：2004-05-27
申请人： Mark Nightingale
发明人： Mark Nightingale
IPC分类号： H01R13/58 , H02G3/00 , H02G15/007
CPC分类号： H01R13/58 , H02G15/007
摘要： An inverted strain relief for receiving a coaxial cable has a housing with a bore therethrough defining first and second apertures in opposing surfaces of the housing. The bore surface is defined by at least a first radius scribing an arc from the perimeter of the first aperture to the second aperture. A smaller second radius scribes an arc tangential to the arc of the first radius over a portion of the exterior surface of the housing. Alternately, the first and second radii may define the surface of the bore with the second radius extending over a portion of the exterior surface of the housing. The bore in the housing is definable by an additional aperture formed adjacent to the first aperture. The surface of the bore is defined by at least the first radius extending from the perimeters of the adjacent apertures.
摘要翻译：用于接收同轴电缆的反向应变消除装置具有壳体，该壳体具有穿过其中的孔，其在壳体的相对表面中限定第一和第二孔。孔表面由至少第一半径限定，该第一半径从第一孔的周边到第二孔划出弧。较小的第二半径在外壳的外表面的一部分上划出与第一半径的弧相切的弧。或者，第一和第二半径可以限定孔的表面，其中第二半径在外壳的外表面的一部分上延伸。壳体中的孔可由邻近第一孔形成的另外的孔限定。孔的表面至少由相邻孔的周边延伸的第一半径限定。

3. 外观设计

USD334147S Electrical test probe 失效
公开(公告)号：USD334147S
公开(公告)日：1993-03-23
申请号：US538941
申请日：1990-06-13
申请人： Glen Aukstikalnis , Mark Nightingale
设计人： Glen Aukstikalnis , Mark Nightingale

4. 发明授权

US08180620B2 Apparatus and method for performing hardware and software co-verification testing 有权
标题翻译：用于执行硬件和软件协同验证测试的装置和方法
公开(公告)号：US08180620B2
公开(公告)日：2012-05-15
申请号：US10764495
申请日：2004-01-27
申请人： Andrew Mark Nightingale
发明人： Andrew Mark Nightingale
IPC分类号： G06F17/50
CPC分类号： G06F11/3672
摘要： Verification tests perform hardware and software co-verification on a system under verification. Each signal interface controller coupled to the system performs a test action transferring at least one of stimulus signals and response signals between a corresponding portion of the system under verification and the signal interface controller during verification. A debugger controls an associated processing unit that executes software routines. A debugger signal interface controller performs test actions transferring stimulus signals and response signals between the debugger and the debugger signal interface controller during verification. A test manager transfers test controlling messages to these interface controllers identifying the test actions to be performed. As a result, the test manager controls the processing unit via the debugger signal interface controller and the debugger in order to coordinate the execution of the software routines with a sequence of verification tests.
摘要翻译：验证测试在验证的系统上执行硬件和软件协同验证。耦合到系统的每个信号接口控制器执行测试动作，以在验证期间在被检测系统的对应部分和信号接口控制器之间传送刺激信号和响应信号中的至少一个。调试器控制执行软件例程的关联处理单元。调试器信号接口控制器在验证期间执行测试动作，在调试器和调试器信号接口控制器之间传送激励信号和响应信号。测试管理器将测试控制消息传送到这些接口控制器，以识别要执行的测试动作。因此，测试管理器通过调试器信号接口控制器和调试器来控制处理单元，以便通过一系列验证测试协调软件程序的执行。

5. 发明申请

US20090070493A1 Interconnect component and device configuration generation 审中-公开
标题翻译：互连组件和设备配置生成
公开(公告)号：US20090070493A1
公开(公告)日：2009-03-12
申请号：US12222449
申请日：2008-08-08
申请人： Peter Andrew Riocreux , Andrew Mark Nightingale
发明人： Peter Andrew Riocreux , Andrew Mark Nightingale
IPC分类号： G06F3/00
CPC分类号： G06F17/5045
摘要： A method of generating a configuration of an integrated circuit 2 having an interconnect component 14 connecting a plurality of devices 4, 6, 8, 10, 12 uses selecting a device to be connected to the interconnect component, reading interface parameters of that device from a file or model (e.g. IP-XACT), selecting parameters of an interface “if” of the interconnect component to match the read parameters, detecting and making any settings in the configuration of the interconnect component 14 itself required to match the selected parameters of the interface and then detecting any changes required in the configuration of any devices previously connected to the interconnect component required to match the configuration of the interconnect component as it now stands. In this way, configuration of the interconnect component can be at least semi-automated with a reduction in the possibility of errors and an increase in the speed of such configuration.
摘要翻译：产生具有连接多个设备4,6,8,10,12的互连部件14的集成电路2的配置的方法使用选择要连接到互连部件的设备，从该设备的接口参数从文件或模型（例如IP-XACT），选择互连组件的接口“if”的参数以匹配读取的参数，检测并进行互连组件14本身的配置中的任何设置，以使其匹配所选择的参数接口，然后检测配置以前连接到互连组件的任何设备所需的任何更改，以匹配互连组件的配置，如现在所示。以这种方式，互连部件的配置可以至少半自动化，同时降低了错误的可能性和这种配置的速度的增加。

6. 发明申请

US20060267602A1 Signal acquisition probe having a retractable double cushioned probing tip assembly 有权
标题翻译：信号采集探头具有可伸缩的双缓冲探测头组件
公开(公告)号：US20060267602A1
公开(公告)日：2006-11-30
申请号：US11139103
申请日：2005-05-27
申请人： Kei-Wean Yang , Mark Nightingale
发明人： Kei-Wean Yang , Mark Nightingale
IPC分类号： G01R31/02
CPC分类号： G01R1/06788 , G01R1/06711
摘要： A signal acquisition probe has a double cushioned spring loaded probing tip assembly disposed in a housing. A first compressive element produces a first pre-loaded compressive force and an increasing compressive force on the probing tip assembly and a second compressive element produces a second pre-loaded compressive force and an increasing compressive force on the probing tip assembly subsequent to the first increasing compressive force. First and second double cushioned spring loaded probing tip assemblies may be disposed in a housing to produce a differential signal acquisition probe.
摘要翻译：信号采集探针具有设置在壳体中的双缓冲弹簧加载探测尖端组件。第一压缩元件在探测尖端组件上产生第一预加载压缩力和增加的压缩力，并且第二压缩元件在第一增加之后产生第二预加载压缩力和在探测尖端组件上增加的压缩力压缩力。第一和第二双缓冲弹簧加载探测头组件可以设置在壳体中以产生差分信号采集探针。

7. 发明授权

US06876941B2 Testing compliance of a device with a bus protocol 有权
标题翻译：测试设备与总线协议的兼容性
公开(公告)号：US06876941B2
公开(公告)日：2005-04-05
申请号：US10084145
申请日：2002-02-28
申请人： Andrew Mark Nightingale
发明人： Andrew Mark Nightingale
IPC分类号： G06F13/00 , H04L12/26 , H04L12/40 , G06F19/00 , G06F13/14
CPC分类号： H04L43/50
摘要： The present invention provides a system and method for testing compliance of a device with a bus protocol. The method comprises the steps of reading a configuration file containing predetermined parameters identifying the type of device and capabilities of the device, and then employing a configuration engine to dynamically generate a test environment for the device by creating selected test components which are coupled via the bus with a representation of the device to form the test environment, the test components being selected dependent on the configuration file. A test sequence is then executed, during which signals passed between the representation of the device and one or more of the test components are monitored to generate result data indicating compliance with the bus protocol. This approach has been found to provide a particularly user friendly and efficient approach for testing compliance of devices with a bus protocol.
摘要翻译：本发明提供一种用于测试设备与总线协议的符合性的系统和方法。该方法包括以下步骤：读取包含标识设备类型和设备能力的预定参数的配置文件，然后采用配置引擎通过创建经由总线耦合的所选择的测试组件动态地为设备生成测试环境以表示设备形成测试环境，测试组件根据配置文件进行选择。然后执行测试序列，在此期间监视在设备的表示和一个或多个测试组件之间传递的信号，以生成指示符合总线协议的结果数据。已经发现这种方法提供了用于测试具有总线协议的设备的兼容性的特别用户友好和有效的方法。

8. 发明授权

US07979822B2 Apparatus and method for performing a sequence of verification tests to verify a design of a data processing system 有权
标题翻译：用于执行一系列验证测试以验证数据处理系统的设计的装置和方法
公开(公告)号：US07979822B2
公开(公告)日：2011-07-12
申请号：US12155337
申请日：2008-06-03
申请人： Andrew Mark Nightingale , Louise Margaret Jameson
发明人： Andrew Mark Nightingale , Louise Margaret Jameson
IPC分类号： G06F17/50
CPC分类号： G06F11/261 , G06F17/5022
摘要： An apparatus and method are provided for performing a sequence of verification tests to verify the design of a data processing system. The apparatus comprises a system under verification representing the design of the data processing system, the system under verification including a component model representing at least one hardware component of the data processing system. The component model includes an interface module through which the component model interacts with other portions of the system under verification during performance of the verification tests. An alternative model is provided for representing the hardware component for selected verification tests, and the interface module comprises a verification interface module which is responsive to switch criteria specified by the alternative model to switch in the alternative model in place of the component model. Accordingly, by such an approach, the alternative model can take the place of the component model during performance of the selected verification tests. This maintains system integrity of the system under verification, whilst providing a simple and effective mechanism for enabling the alternative model to take the place of the component model for certain specific verification tests, for example when testing corner cases in the design.
摘要翻译：提供了一种用于执行验证测试序列以验证数据处理系统的设计的装置和方法。该装置包括正在验证的表示数据处理系统的设计的系统，该验证系统包括表示数据处理系统的至少一个硬件部件的组件模型。组件模型包括一个接口模块，组件模型在执行验证测试期间通过该接口模块与系统的其他部分进行验证。提供了用于表示用于所选验证测试的硬件组件的替代模型，并且接口模块包括验证接口模块，该验证接口模块响应于替代模型指定的切换标准来切换替代模型而不是组件模型。因此，通过这种方法，替代模型可以在执行选定的验证测试期间代替组件模型。这将维护系统的系统完整性，同时提供一种简单有效的机制，使替代模型能够代替某些特定验证测试的组件模型，例如在设计中测试角落时。

9. 发明授权

US07856346B2 Emulating multiple bus used within a data processing system 有权
标题翻译：仿真数据处理系统中使用的多个总线
公开(公告)号：US07856346B2
公开(公告)日：2010-12-21
申请号：US10142148
申请日：2002-05-10
申请人： Andrew Mark Nightingale , Timothy Charles Mace
发明人： Andrew Mark Nightingale , Timothy Charles Mace
IPC分类号： G06F19/00 , G06F17/50 , G06F9/44 , G06F9/455 , G01R27/28 , G04F5/00
CPC分类号： G06F17/5022 , G06F11/261
摘要： A test system for data processing circuit design emulates multiple bus masters and provides an arbitration mechanism for coordinating arbitration between those bus masters in the design emulation. The shared bus being tested may be a multi-layer bus and one or more of the bus masters being emulated or bus slaves being emulated may be cut-down emulations modelling the bus interaction itself or full emulations of the intended bus master circuit or bus slave circuit including its operational data processing.
摘要翻译：一种用于数据处理电路设计的测试系统模拟多个总线主机，并提供了一种仲裁机制，用于协调设计仿真中那些总线主机之间的仲裁。正在测试的共享总线可以是多层总线，并且仿真的总线主机中的一个或多个或正在仿真的总线从机可以是模拟总线交互本身的模拟仿真或预期的总线主电路或总线从站的全部仿真电路包括其操作数据处理。

10. 发明授权

US07761280B2 Data processing apparatus simulation by generating anticipated timing information for bus data transfers 有权
标题翻译：通过产生总线数据传输的预期定时信息来进行数据处理装置的仿真
公开(公告)号：US07761280B2
公开(公告)日：2010-07-20
申请号：US10802032
申请日：2004-03-17
申请人： Andrew Mark Nightingale , Daren Croxford
发明人： Andrew Mark Nightingale , Daren Croxford
IPC分类号： G06G7/62 , G06F17/50
CPC分类号： G06F17/5031
摘要： Simulation of the operation of a data processing apparatus having a number of master logic units and slave logic units coupled via a bus is provided. The data processing apparatus performs data transfers between the master logic units and the slave logic units over the bus. Anticipated timing information for each successive data transfer over the bus is generated by assuming that each successive data transfer can occur with exclusive access to the bus, determining whether the anticipated timing information indicates that two or more concurrent data transfers would occur on the bus, and in the event that the anticipated timing information indicates that two or more concurrent data transfers would occur on the bus, generating revised timing information for those data transfers, the revised timing information being generated using bus status information until those data transfers have been completed.
摘要翻译：提供了具有通过总线耦合的多个主逻辑单元和从属逻辑单元的数据处理装置的操作的仿真。数据处理装置通过总线执行主逻辑单元和从属逻辑单元之间的数据传送。通过假定每次连续数据传输可以通过对总线的独占访问发生，确定预期的定时信息是否指示在总线上发生两个或更多个并行数据传输来产生通过总线的每个连续数据传送的预期定时信息，以及在预期定时信息指示在总线上发生两个或多个并行数据传输的情况下，生成用于那些数据传输的修正定时信息，修正的定时信息是使用总线状态信息生成的，直到那些数据传送已经完成。

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