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1. 发明申请

US20100188729A1 Ceramic Header Method and System 有权
标题翻译：陶瓷头头法和系统
公开(公告)号：US20100188729A1
公开(公告)日：2010-07-29
申请号：US12752363
申请日：2010-04-01
申请人： Moody K. Forgey , Mark A. Kressley
发明人： Moody K. Forgey , Mark A. Kressley
IPC分类号： G02B26/00 , B23K26/00 , B24B1/00 , H05K3/30 , H05K5/02
CPC分类号： H01L21/4807 , B81C1/00333 , H01L23/10 , H01L23/15 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2924/01079 , H01L2924/09701 , H01L2924/1461 , Y10T29/49005 , Y10T29/4908 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , Y10T29/49297 , H01L2924/00014 , H01L2924/00
摘要： A ceramic header configured to form a portion of an electronic device package includes a mounting portion configured to provide a mounting surface for an electronic device. In addition, the ceramic header includes one or more conductive input-output connectors operable to provide electrical connections from a first surface of the ceramic header to a second surface of the ceramic header. The ceramic header also includes one or more thermally polished surfaces.
摘要翻译：构造成形成电子器件封装的一部分的陶瓷接头包括构造成提供用于电子器件的安装表面的安装部分。此外，陶瓷集管包括一个或多个导电输入 - 输出连接器，其可操作以提供从陶瓷集管的第一表面到陶瓷集管的第二表面的电连接。陶瓷集管还包括一个或多个热抛光表面。

2. 发明授权

US08627566B2 Method for packaging a microelectromechanical system (MEMS) device 有权
标题翻译：用于封装微机电系统（MEMS）装置的方法
公开(公告)号：US08627566B2
公开(公告)日：2014-01-14
申请号：US12752363
申请日：2010-04-01
申请人： Moody K. Forgey , Mark A. Kressley
发明人： Moody K. Forgey , Mark A. Kressley
IPC分类号： B21D53/84
CPC分类号： H01L21/4807 , B81C1/00333 , H01L23/10 , H01L23/15 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2924/01079 , H01L2924/09701 , H01L2924/1461 , Y10T29/49005 , Y10T29/4908 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , Y10T29/49297 , H01L2924/00014 , H01L2924/00
摘要： A ceramic header configured to form a portion of an electronic device package includes a mounting portion configured to provide a mounting surface for an electronic device. In addition, the ceramic header includes one or more conductive input-output connectors operable to provide electrical connections from a first surface of the ceramic header to a second surface of the ceramic header. The ceramic header also includes one or more thermally polished surfaces.
摘要翻译：构造成形成电子器件封装的一部分的陶瓷接头包括构造成提供用于电子器件的安装表面的安装部分。此外，陶瓷集管包括一个或多个导电输入 - 输出连接器，其可操作以提供从陶瓷集管的第一表面到陶瓷集管的第二表面的电连接。陶瓷集管还包括一个或多个热抛光表面。

3. 发明授权

US06600183B1 Integrated circuit capacitor and memory 失效
标题翻译：集成电路电容和存储器
公开(公告)号：US06600183B1
公开(公告)日：2003-07-29
申请号：US09105830
申请日：1998-06-26
申请人： Mark R. Visokay , Luigi Colombo , Rajesh Khamankar , Mark A. Kressley
发明人： Mark R. Visokay , Luigi Colombo , Rajesh Khamankar , Mark A. Kressley
IPC分类号： H01L2976
CPC分类号： H01L21/7685 , H01L21/32136 , H01L21/32139 , H01L21/76802 , H01L21/7687 , H01L21/76889 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： An electrode structure for a capacitor. The electrode structure includes a contact plug comprising an oxidation barrier 208 and a bottom electrode comprising a conductive adhesion-promoting portion 210 and an oxidation-resistant portion 204, the adhesion-promoting portion contacting the oxidation barrier of the contact plug. In further embodiments, the oxidation barrier and adhesion-promoting portion comprise Ti—Al—N.
摘要翻译：电容器的电极结构。电极结构包括接触塞，其包括氧化屏障208和包括导电粘附促进部分210和抗氧化部分204的底部电极，所述粘合促进部分接触接触插塞的氧化屏障。在另外的实施方案中，氧化屏障和增粘部分包括Ti-Al-N。

4. 发明申请

US20080099240A1 Ceramic header method and system 有权
标题翻译：陶瓷头法和系统
公开(公告)号：US20080099240A1
公开(公告)日：2008-05-01
申请号：US11586366
申请日：2006-10-25
申请人： Moody K. Forgey , Mark A. Kressley
发明人： Moody K. Forgey , Mark A. Kressley
IPC分类号： H01L23/02
CPC分类号： H01L21/4807 , B81C1/00333 , H01L23/10 , H01L23/15 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2924/01079 , H01L2924/09701 , H01L2924/1461 , Y10T29/49005 , Y10T29/4908 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , Y10T29/49297 , H01L2924/00014 , H01L2924/00
摘要： A ceramic header configured to form a portion of an electronic device package includes a mounting portion configured to provide a mounting surface for an electronic device. In addition, the ceramic header includes one or more conductive input-output connectors operable to provide electrical connections from a first surface of the ceramic header to a second surface of the ceramic header. The ceramic header also includes one or more thermally polished surfaces.
摘要翻译：构造成形成电子器件封装的一部分的陶瓷接头包括构造成提供用于电子器件的安装表面的安装部分。此外，陶瓷集管包括一个或多个导电输入 - 输出连接器，其可操作以提供从陶瓷集管的第一表面到陶瓷集管的第二表面的电连接。陶瓷集管还包括一个或多个热抛光表面。

5. 发明授权

US07690106B2 Ceramic header method 有权
标题翻译：陶瓷头法
公开(公告)号：US07690106B2
公开(公告)日：2010-04-06
申请号：US11586366
申请日：2006-10-25
申请人： Moody K. Forgey , Mark A. Kressley
发明人： Moody K. Forgey , Mark A. Kressley
IPC分类号： H05K3/30 , H01L21/00
CPC分类号： H01L21/4807 , B81C1/00333 , H01L23/10 , H01L23/15 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2924/01079 , H01L2924/09701 , H01L2924/1461 , Y10T29/49005 , Y10T29/4908 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , Y10T29/49297 , H01L2924/00014 , H01L2924/00
摘要： A ceramic header configured to form a portion of an electronic device package includes a mounting portion configured to provide a mounting surface for an electronic device. In addition, the ceramic header includes one or more conductive input-output connectors operable to provide electrical connections from a first surface of the ceramic header to a second surface of the ceramic header. The ceramic header also includes one or more thermally polished surfaces.
摘要翻译：构造成形成电子器件封装的一部分的陶瓷接头包括构造成提供用于电子器件的安装表面的安装部分。此外，陶瓷集管包括一个或多个导电输入 - 输出连接器，其可操作以提供从陶瓷集管的第一表面到陶瓷集管的第二表面的电连接。陶瓷集管还包括一个或多个热抛光表面。

6. 发明授权

US5646068A Solder bump transfer for microelectronics packaging and assembly 失效
标题翻译：焊接凸块转移用于微电子封装和组装
公开(公告)号：US5646068A
公开(公告)日：1997-07-08
申请号：US384506
申请日：1995-02-03
申请人： Arthur M. Wilson , Mark A. Kressley , Dean L. Frew , Juanita G. Miller , John E. Hanicak , Philip E. Hecker , James M. Drumm
发明人： Arthur M. Wilson , Mark A. Kressley , Dean L. Frew , Juanita G. Miller , John E. Hanicak , Philip E. Hecker , James M. Drumm
IPC分类号： H01L21/48 , H01L21/60 , H01L21/68 , H01L23/498 , H01L25/065 , H05K3/34 , H01L21/44
CPC分类号： H01L24/12 , H01L21/4853 , H01L21/6835 , H01L23/49816 , H01L24/11 , H01L25/0652 , H05K3/3473 , H01L2224/13099 , H01L2224/45144 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H05K2203/016 , H05K2203/0338 , H05K2203/043 , H05K2203/0726
摘要： A method of making a microelectronic circuit and the connection pattern therefor including the steps of providing a substrate (3), preferably silicon and preferably including a layer of nickel (38) under a layer of gold (36) thereon. Regions are formed on the substrate for connection of electrical components to the substrate using a first metallurgy, preferably gold and a pattern of bumps (5, 7) is formed of a second metallurgy different from the first metallurgy, preferably lead/tin solder. An interconnection pattern is formed on the substrate contacting at least one bump and at least one pad. The pattern of solder bumps is formed by providing a coupon (31) and patterning the bumps on the coupon and applied to the substrate while attached to the coupon, then heated to cause flow of the bumps onto the substrate. The coupon is then removed from the bumps with the bumps remaining on the substrate. Electrical components are applied to the region of first metallurgy and electrically bonded by wire bonding or Tape Automated Bonding techniques. Electrical components are applied to the region of the second metallurgy and electrically bonded by flip-chip technique.
摘要翻译：一种制造微电子电路的方法及其连接图案包括以下步骤：提供衬底（3），优选硅，并且优选地包括在其上的金层（36）下方的一层镍（38）。区域形成在基板上，用于使用第一冶金将电气部件连接到基板，优选金和凸起图案（5,7）由不同于第一冶金，优选铅/锡焊料的第二冶金形成。在与至少一个凸块和至少一个焊盘接触的衬底上形成互连图案。焊料凸块的图案通过提供优惠券（31）并且在附件上图案化凸起并施加到基板上而形成，然后加热以使凸块流到基板上。然后从凸块上取出试样，凸块残留在基片上。电气部件应用于第一冶金领域，并通过引线接合或磁带自动键合技术进行电接合。电气部件被施加到第二冶金的区域并通过倒装芯片技术电连接。

7. 发明授权

US5558554A Method for fabricating a field emission device anode plate having multiple grooves between anode conductors 失效
标题翻译：用于制造在阳极导体之间具有多个凹槽的场致发射器件阳极板的方法
公开(公告)号：US5558554A
公开(公告)日：1996-09-24
申请号：US455312
申请日：1995-05-31
申请人： John E. Finklea , Chi-Cheong Shen , Kenneth G. Vickers , Mark A. Kressley
发明人： John E. Finklea , Chi-Cheong Shen , Kenneth G. Vickers , Mark A. Kressley
IPC分类号： H01J9/14 , H01J29/08 , H01J9/20
CPC分类号： H01J9/148 , H01J29/085
摘要： A method of fabricating an anode plate 40 having a multiplicity of grooves 50 for use in a field emission flat panel display device comprises the steps of providing a transparent planar substrate 42 having a plurality of electrically conductive, parallel stripes 46 comprising the anode electrode of the device; etching a plurality of grooves 50 in the surface of the substrate in the spaces between the stripes 46; and then applying phosphor material 48.sub.R, 48.sub.G and 48.sub.B over the stripes 46. In one embodiment, a plurality of grooves 50', having generally vertical sidewalls, are formed in the upper surface of planar substrate 42' at the interstices of conductors 46. In a second embodiment, a plurality of grooves 50", having generally curved sidewalls, are formed in the upper surface of planar substrate 42' at the interstices of conductors 46'. In a third embodiment, a plurality of grooves 50", having generally vertical sidewalls, are formed in the upper surface of an insulating material 52 located between conductors 46". In a fourth embodiment, a plurality of grooves 50'", having generally curved sidewalls, are formed in the upper surface of an insulating material 52' between conductors 46'". In a fifth embodiment, a plurality of grooves are formed in the upper surface of planar substrate 100, and insulating material 108 is applied over the grooves. In a sixth embodiment, a plurality of grooves are formed in both the surface of the planar substrate 120 and the surface of insulating material 128.
摘要翻译：一种制造具有用于场发射平板显示装置中的多个凹槽50的阳极板40的方法包括以下步骤：提供具有多个导电平行条纹46的透明平面基板42，所述多个导电平行条纹46包括：设备; 在条纹46之间的空间中蚀刻衬底表面中的多个凹槽50; 然后将荧光材料48R，48G和48B施加在条纹46上。在一个实施例中，在导体46的间隙处，在平面基底42'的上表面中形成多个具有大致垂直侧壁的凹槽50'。在第二实施例中，在导体46'的间隙处在平面基板42'的上表面中形成具有大体弯曲的侧壁的多个凹槽50“。在第三实施例中，在位于导体46“之间的绝缘材料52的上表面中形成有具有大致垂直侧壁的多个凹槽50”。在第四实施例中，在导体46“之间的绝缘材料52'的上表面上形成有多个具有大致弯曲侧壁的槽50”'。在第五实施例中，在平面基板100的上表面中形成多个槽，并且在槽上施加绝缘材料108。在第六实施例中，在平面基板120的表面和绝缘材料128的表面上形成多个槽。

8. 发明授权

US5327327A Three dimensional assembly of integrated circuit chips 失效
标题翻译：集成电路芯片的三维组装
公开(公告)号：US5327327A
公开(公告)日：1994-07-05
申请号：US969602
申请日：1992-10-30
申请人： Dean L. Frew , Mark A. Kressley , Arthur M. Wilson , Juanita G. Miller , Philip E. Hecker, Jr. , James Drumm , Randall E. Johnson , Rick Elder
发明人： Dean L. Frew , Mark A. Kressley , Arthur M. Wilson , Juanita G. Miller , Philip E. Hecker, Jr. , James Drumm , Randall E. Johnson , Rick Elder
IPC分类号： H01L25/065 , H05K1/11
CPC分类号： H01L25/0657 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06579 , H01L2924/0002
摘要： The multi-chip circuit module of the invention comprises a plurality of circuit chips assembled in a laminated stack. Each chip includes a plurality of layers of thin film interconnect patterns in the normal configuration, except for the final layer or layers, which comprise a reroute pattern that locates all circuit input and output pads along a single edge of each chip. The relocated pads are provided with contact bumps to facilitate the addition of a bonded lead to each I/O pad extending therefrom to a point beyond the edge of each chip. Thus, upon lamination the protruding tips form an array of leads on a single lateral face of the laminated chip stack.
摘要翻译：本发明的多芯片电路模块包括组装在层叠叠层中的多个电路芯片。每个芯片包括正常配置中的多层薄膜互连图案，除了最终层或层，其包括沿着每个芯片的单个边缘定位所有电路输入和输出焊盘的重新布线图案。重新定位的焊盘设置有接触凸块，以便于将结合引线添加到从其延伸到每个芯片边缘的点的每个I / O焊盘。因此，在叠层时，突出的尖端在层压芯片堆叠的单个侧面上形成引线阵列。

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