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1. 发明授权

US08258821B2 Multi-voltage input buffer 有权
标题翻译：多电压输入缓冲器
公开(公告)号：US08258821B2
公开(公告)日：2012-09-04
申请号：US12959142
申请日：2010-12-02
申请人： Marius V. Dina , Jeremy R. Kuehlwein
发明人： Marius V. Dina , Jeremy R. Kuehlwein
IPC分类号： H03K3/00
CPC分类号： H03K19/017518
摘要： In hard disc drive (HDD) applications, there is often a need for input buffers that can operate at a variety of voltages (i.e., 1.8V, 2.5V, and 3.3V) as well as tolerate high voltages (i.e., 5V). Traditional buffers, however, usually lack the ability to operate at these varying voltages and lack the ability to tolerate high voltages. Here, a buffer is provided that fits this criteria through the use of a switching circuit and an anti-saturation circuit (as well as other circuitry).
摘要翻译：在硬盘驱动器（HDD）应用中，通常需要能够以各种电压（即1.8V，2.5V和3.3V）工作以及容忍高电压（即5V）的输入缓冲器。然而，传统的缓冲器通常缺乏在这些变化的电压下操作的能力，并且缺乏耐受高电压的能力。这里提供了通过使用开关电路和抗饱和电路（以及其它电路）来适应该标准的缓冲器。

2. 发明授权

US5787094A Test and diagnostics for a self-timed parallel interface 失效
标题翻译：自定时并行接口的测试和诊断
公开(公告)号：US5787094A
公开(公告)日：1998-07-28
申请号：US656950
申请日：1996-06-06
申请人： Delbert Raymond Cecchi , Marius V. Dina , Curtis Walter Preuss , Kenneth Michael Valk
发明人： Delbert Raymond Cecchi , Marius V. Dina , Curtis Walter Preuss , Kenneth Michael Valk
IPC分类号： G06F11/263 , G06F11/267 , G06F11/10 , H03M13/00
CPC分类号： G06F11/221 , G01R31/318385 , G06F11/263
摘要： A method and apparatus that can test self-timed parallel interfaces operating at system speed. An output stage is provided for queuing a test packet and providing the test packet to an input stage. The packet contains a data bit stream and error detection code such as cyclic redundancy check code. The input stage is coupled to the output stage and receives the test packet to determine the correctness of the data bit stream. On the input stage, the error detection code verifier recalculates the error detection code and compares the recalculated error detection code with the error detection code attached to the data bit stream to determine the correctness of the data bit steam. The output queue has a first input port for receiving data from drivers on the interface and a second input port for receiving a pseudo random data bit stream. A pseudo random data generator generates a pseudo random data bit stream. The data bit stream may be packetized according to a predetermined protocol. An off-chip signal of the output stage may be provided to the inputs of the input stage to produce an on-chip copy of off-chip data.
摘要翻译：可以测试以系统速度运行的自定时并行接口的方法和装置。提供输出级用于排队测试分组并将测试分组提供给输入级。分组包含数据比特流和诸如循环冗余校验码的错误检测码。输入级耦合到输出级并接收测试数据包以确定数据位流的正确性。在输入级上，错误检测码验证器重新计算错误检测码，并将重新计算的错误检测码与附加到数据比特流的错误检测码进行比较，以确定数据比特流的正确性。输出队列具有用于从接口上的驱动器接收数据的第一输入端口和用于接收伪随机数据位流的第二输入端口。伪随机数据生成器生成伪随机数据比特流。可以根据预定协议对数据比特流进行分组化。可以将输出级的片外信号提供给输入级的输入，以产生片外数据的片上拷贝。

3. 发明申请

US20120139606A1 MULTI-VOLTAGE INPUT BUFFER 有权
标题翻译：多电平输入缓冲器
公开(公告)号：US20120139606A1
公开(公告)日：2012-06-07
申请号：US12959142
申请日：2010-12-02
申请人： Marius V. Dina , Jeremy R. Kuehlwein
发明人： Marius V. Dina , Jeremy R. Kuehlwein
IPC分类号： H03L5/00
CPC分类号： H03K19/017518
摘要： In hard disc drive (HDD) applications, there is often a need for input buffers that can operate at a variety of voltages (i.e., 1.8V, 2.5V, and 3.3V) as well as tolerate high voltages (i.e., 5V). Traditional buffers, however, usually lack the ability to operate at these varying voltages and lack the ability to tolerate high voltages. Here, a buffer is provided that fits this criteria through the use of a switching circuit and an anti-saturation circuit (as well as other circuitry).
摘要翻译：在硬盘驱动器（HDD）应用中，通常需要能够以各种电压（即1.8V，2.5V和3.3V）工作以及容忍高电压（即5V）的输入缓冲器。然而，传统的缓冲器通常缺乏在这些变化的电压下操作的能力，并且缺乏耐受高电压的能力。这里提供了通过使用开关电路和抗饱和电路（以及其它电路）来适应该标准的缓冲器。

4. 发明申请

US20100315917A1 INPUT CURRENT CHANNEL DEVICE 有权
标题翻译：输入电流通道
公开(公告)号：US20100315917A1
公开(公告)日：2010-12-16
申请号：US12622559
申请日：2009-11-20
申请人： Shengyuan Li , Indumini W. Ranmuthu , Marius V. Dina
发明人： Shengyuan Li , Indumini W. Ranmuthu , Marius V. Dina
IPC分类号： G11B20/10
CPC分类号： G11B7/126 , G11B7/00456
摘要： An input current channel device is described. This device comprises a first terminal for receiving a reference signal; a second terminal for receiving a first target signal; a pass through device coupled to the first terminal, the pass through device operative for transmitting a delayed reference signal in response to receiving the reference signal; a first combination logic device coupled to the first terminal and the second terminal, the first combination logic device operative for transmitting a first combination logic signal in response to receiving the reference signal and the first target signal; a selection device coupled for receiving the delayed reference signal, the first combination logic signal, and a first synchronization signal, the selection device operative for selectively transmitting a second synchronization signal, and wherein selectively transmitting the second synchronization signal reduces skew between the reference channel and the first target channel.
摘要翻译：描述输入电流通道器件。该装置包括用于接收参考信号的第一端子; 用于接收第一目标信号的第二终端; 耦合到所述第一终端的通过设备，所述通过设备用于响应于接收到所述参考信号而发送延迟的参考信号; 耦合到所述第一终端和所述第二终端的第一组合逻辑设备，所述第一组合逻辑设备用于响应于接收到所述参考信号和所述第一目标信号而发送第一组合逻辑信号; 耦合用于接收所述延迟的参考信号的选择装置，所述第一组合逻辑信号和第一同步信号，所述选择装置用于选择性地发送第二同步信号，并且其中选择性地发送所述第二同步信号减少所述参考信道和第一个目标通道。

5. 发明授权

US08174953B2 Input current channel device 有权
标题翻译：输入电流通道器件
公开(公告)号：US08174953B2
公开(公告)日：2012-05-08
申请号：US12622559
申请日：2009-11-20
申请人： Shengyuan Li , Indumini W. Ranmuthu , Marius V. Dina
发明人： Shengyuan Li , Indumini W. Ranmuthu , Marius V. Dina
IPC分类号： G11B7/00
CPC分类号： G11B7/126 , G11B7/00456
摘要： An input current channel device is described. This device comprises a first terminal for receiving a reference signal; a second terminal for receiving a first target signal; a pass through device coupled to the first terminal, the pass through device operative for transmitting a delayed reference signal in response to receiving the reference signal; a first combination logic device coupled to the first terminal and the second terminal, the first combination logic device operative for transmitting a first combination logic signal in response to receiving the reference signal and the first target signal; a selection device coupled for receiving the delayed reference signal, the first combination logic signal, and a first synchronization signal, the selection device operative for selectively transmitting a second synchronization signal, and wherein selectively transmitting the second synchronization signal reduces skew between the reference channel and the first target channel.
摘要翻译：描述输入电流通道器件。该装置包括用于接收参考信号的第一端子; 用于接收第一目标信号的第二终端; 耦合到所述第一终端的通过设备，所述通过设备响应于接收到所述参考信号而用于发送延迟的参考信号; 耦合到所述第一终端和所述第二终端的第一组合逻辑设备，所述第一组合逻辑设备用于响应于接收到所述参考信号和所述第一目标信号而发送第一组合逻辑信号; 耦合用于接收所述延迟参考信号的选择装置，所述第一组合逻辑信号和第一同步信号，所述选择装置用于选择性地发送第二同步信号，并且其中选择性地发送所述第二同步信号减少所述参考信道和第一个目标通道。

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