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1. 发明授权

US5159423A Self-aligned, planar heterojunction bipolar transistor 失效
标题翻译：自对准平面异质结双极晶体管
公开(公告)号：US5159423A
公开(公告)日：1992-10-27
申请号：US702211
申请日：1991-05-17
申请人： Marion D. Clark , William E. Stanchina , K. Vaidyanathan
发明人： Marion D. Clark , William E. Stanchina , K. Vaidyanathan
IPC分类号： H01L21/28 , H01L21/331 , H01L29/737
CPC分类号： H01L29/66318 , H01L21/28 , H01L29/7371
摘要： A heterojunction bipolar transistor (HBT) is formed with self-aligned base-emitter and base-collector junctions by forming a two-level mask over a doped base layer, sequentially forming openings in registration through the two mask layers, and using the opening in one mask layer to define the collector region and the opening in the other mask layer to define the emitter. A buried conductive layer formed by a dopant implant establishes an electrical contact to the collector region, and connects to the surface via another conductive implant that extends through a lateral extension of the collector region. The collector region itself is formed by a dopant implant, while the active base region which forms junctions with the emitter and collector is thinner than the remainder of the base layer; the latter feature reduces the resistivity associated with connections to lateral base contacts. Parasitic capacitances are minimized when the collector and buried conductive layers are implanted into a semi-insulating substrate such that only the active junction regions overlap.
摘要翻译：异质结双极晶体管（HBT）通过在掺杂的基底层上形成二级掩模而顺序地形成通过两个掩模层配准的开口，并且使用开口一个掩模层，以限定集电极区域和另一个掩模层中的开口以限定发射极。由掺杂剂注入形成的掩埋导电层建立与集电极区的电接触，并通过延伸通过集电极区的横向延伸的另一个导电注入连接到表面。集电极区域本身由掺杂剂注入形成，而与发射极和集电极形成结的有源基极区域比基极层的其余部分薄; 后者的特征降低了与横向基底触点的连接性相关联的电阻率。当将集电极和掩埋导电层注入半绝缘衬底中使得只有活性连接区重叠时，寄生电容被最小化。

2. 发明授权

US4733927A Stress waveguides in bulk crystalline materials 失效
标题翻译：应力波导在块状结晶材料中
公开(公告)号：US4733927A
公开(公告)日：1988-03-29
申请号：US671523
申请日：1984-11-14
申请人： Deborah J. Jackson , Marion D. Clark
发明人： Deborah J. Jackson , Marion D. Clark
IPC分类号： G02B6/12 , G02B6/122 , G02F1/025 , G02B6/10
CPC分类号： G02B6/122 , G02F1/025
摘要： An optical waveguide is established near the surface of a body of bulk, optically transparent, crystalline material (12) by depositing and bonding a thin layer of material (16) that undergoes an irreversible structural transition under annealing such as silicon nitride or silicon oxide on a surface of the bulk crystalline material (12). The assembly is then heated to change the state of the thin layer and produce stress on the order of 10.sup.10 to 10.sup.11 dynes per square centimeter or more. Open guideways or breaks (22, 24) are then formed in the thin layer (16), thereby establishing optical stress waveguides (32, 34) in the bulk crystalline material (12), just under the open guideways. The bulk crystalline material is then employed for modulation, detection or in other interactive processes with respect to optical signals applied to the waveguide.
摘要翻译：通过在诸如氮化硅或氧化硅的退火处经历不可逆的结构转变的薄层材料（16）沉积和结合，在体，光学透明的结晶材料（12）的表面附近建立光波导，块状结晶材料（12）的表面。然后将组件加热以改变薄层的状态并产生约10 1至10 11达因/平方厘米或更大的应力。然后在薄层（16）中形成打开的导轨或断裂（22,24），从而在刚开放的导轨下方在本体结晶材料（12）中建立光应力波导（32,34）。然后，本体结晶材料用于相对于施加到波导的光信号的调制，检测或其它交互过程。

3. 发明授权

US5098853A Self-aligned, planar heterojunction bipolar transistor and method of forming the same 失效
标题翻译：自对准的平面异相双极晶体管及其形成方法
公开(公告)号：US5098853A
公开(公告)日：1992-03-24
申请号：US266378
申请日：1988-11-02
申请人： Marion D. Clark , William E. Stanchina , K. Vaidyanathan
发明人： Marion D. Clark , William E. Stanchina , K. Vaidyanathan
IPC分类号： H01L21/28 , H01L21/331 , H01L29/737
CPC分类号： H01L29/66318 , H01L21/28 , H01L29/7371
摘要： A heterojunction bipolar transistor (HBT) is formed with self-aligned base-emitter and base-collector junctions by forming a two-level mask over a doped base layer, sequentially forming openings in registration through the two mask layers, and using the opening in one mask layer to define the collector region and the opening in the other mask layer to define the emitter. A buried conductive layer formed by a dopant implant establishes an electrical contact to the collector region, and connects to the surface via another conductive implant that extends through a lateral extension of the collector region. The collector region itself is formed by a dopant implant, while the active base region which forms junctions with the emitter and collector is thinner than the remainder of the base layer; the latter feature reduces the resistivity associated with connection to lateral base contacts. Parasitic capacitances are minimized when the collector and buried conductive layers are implanted into a semi-insulating substrate such that only the active junction regions overlap.
摘要翻译：异质结双极晶体管（HBT）通过在掺杂的基底层上形成二级掩模而顺序地形成通过两个掩模层配准的开口，并且使用开口一个掩模层，以限定集电极区域和另一个掩模层中的开口以限定发射极。由掺杂剂注入形成的掩埋导电层建立与集电极区的电接触，并通过延伸通过集电极区的横向延伸的另一个导电注入连接到表面。集电极区域本身由掺杂剂注入形成，而与发射极和集电极形成结的有源基极区域比基极层的其余部分薄; 后者的特征降低了与横向基底触点的连接相关联的电阻率。当将集电极和掩埋导电层注入半绝缘衬底中使得只有活性连接区重叠时，寄生电容被最小化。

4. 发明授权

US4692993A Schottky barrier charge coupled device (CCD) manufacture 失效
标题翻译：肖特基势垒电荷耦合器件（CCD）制造
公开(公告)号：US4692993A
公开(公告)日：1987-09-15
申请号：US784447
申请日：1985-10-04
申请人： Marion D. Clark , C. Lawrence Anderson
发明人： Marion D. Clark , C. Lawrence Anderson
IPC分类号： H01L21/314 , H01L21/764 , H01L21/765 , H01L29/765 , H01L21/24 , H01L29/56
CPC分类号： H01L21/3145 , H01L21/764 , H01L21/765 , H01L29/765
摘要： The specification describes a planar gallium arsenide charge coupled device and process for making same wherein a first series of metal pattern forming steps are performed on the surface of a GaAs semiconductor body to form input, output and bias electrodes of a CCD in a first level or plane of the structure. In a subsequent, second series of metal pattern forming steps, a plurality of charge transfer electrodes are formed between the CCD input and output electrodes, and simultaneously an annular charge isolation electrode is deposited so as to completely surround the input, output, and charge transfer electrodes of the CCD. These electrodes deposited in this second series of metal pattern forming steps lie in a second level or plane of the structure being fabricated. Next, a dielectric mask is formed on the surface of the last named electrodes. Openings ("vias") are formed therein which are aligned with the input, output, charge transfer and charge isolation electrodes. Thereafter, a third series of metal pattern forming steps are utilized to form a plurality of crossover or lead-in electrodes which are deposited in the above openings in the dielectric mask to provide electrical signal and bias coupling to the electrodes formed in the above first and second series of metal pattern forming steps. Thus, by forming the charge isolation electrode simultaneously with the electrodes of the charge coupled device per se, the total number of device fabrication steps are minimized.
摘要翻译：该说明书描述了一种平面砷化镓电荷耦合器件及其制造方法，其中在GaAs半导体器件的表面上执行第一系列金属图案形成步骤，以形成第一级的CCD的输入，输出和偏置电极，平面的结构。在随后的第二系列金属图案形成步骤中，在CCD输入和输出电极之间形成多个电荷转移电极，并且同时沉积环形电荷隔离电极，以完全包围输入，输出和电荷转移 CCD的电极。沉积在该第二系列金属图案形成步骤中的这些电极位于被制造的结构的第二层或平面内。接下来，在最后命名的电极的表面上形成介电掩模。在其中形成开口（“通孔”），其与输入，输出，电荷转移和电荷隔离电极对准。此后，利用第三系列金属图形形成步骤来形成多个交叉或引入电极，这些电极沉积在电介质掩模中的上述开口中，以提供与上述第一和第二电极形成的电极的电信号和偏置耦合，第二系列金属图案形成步骤。因此，通过与电荷耦合器件本身的电极同时形成电荷隔离电极，使器件制造步骤的总数最小化。

5. 发明授权

US4036720A Hydrogen isotope separation 失效
标题翻译：氢同位素分离
公开(公告)号：US4036720A
公开(公告)日：1977-07-19
申请号：US734904
申请日：1976-10-22
申请人： Marion D. Clark , Thomas J. Manuccia
发明人： Marion D. Clark , Thomas J. Manuccia
IPC分类号： C01B4/00 , B01K1/00 , C01B1/28 , C01C1/02
CPC分类号： C01B4/00
摘要： A method of separating isotopes of hydrogen which comprises subjecting a ture of nitrogen and isotopes of hydrogen in a H.sub.2 --N.sub.2 mole ratio from 1:4 to 10:1 to a glow electrical discharge from 10.sup..sup.-3 to 10.sup.+.sup.1 eV per reactant molecules at a temperature from 50.degree. K to 200.degree. K and at a pressure of at least 0.3 Torr.
摘要翻译：一种分离氢的同位素的方法，其包括使氢和氮的同位素的混合物以H 2 -N 2摩尔比为1:4至10:1进行10-3-3-10℃的辉光放电每个反应物分子在50℃至200℃的温度和至少0.3托的压力下进行。

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