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1. 发明申请

US20080040589A1 PROCESSOR DEVICE 有权
标题翻译：处理器件
公开(公告)号：US20080040589A1
公开(公告)日：2008-02-14
申请号：US11875431
申请日：2007-10-19
申请人： Mariko SAKAMOTO , Toshio Yoshida
发明人： Mariko SAKAMOTO , Toshio Yoshida
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/30181 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A processor device having a reservation station (RS) is concerned. In case the processor device has plural RS, the RS is associated with an arithmetic pipeline, and two RS make a pair. When one RS of the pair cannot dispatch an instruction to an associated arithmetic pipeline, the other RS dispatches the instruction to that arithmetic pipeline, or delivers its held instruction to the one RS. In case one RS is equipped, plural entries in the RS are divided into groups, and by dynamically changing this grouping according to the dispatch frequency of the instruction to the arithmetic pipelines or the held state of the instructions, the arithmetic pipelines are efficiently utilized. Incidentally, depending on the grouping of the plural entries in the RS, a configuration as if the plural RS were allocated to each arithmetic pipeline may be realized.
摘要翻译：涉及具有保留站（RS）的处理器设备。在处理器设备具有多个RS的情况下，RS与算术流水线相关联，并且两个RS成对。当该对的一个RS不能向相关联的算术流水线发送指令时，另一个RS将指令发送到该算术流水线，或者将其保持的指令递送到一个RS。在配备一个RS的情况下，RS中的多个条目被分成组，并且通过根据指令的调度频率动态地改变该分组到算术流水线或指令的保持状态，可以有效地利用算术流水线。顺便提及，根据RS中的多个条目的分组，可以实现如同将多个RS分配给每个运算管线的配置。

2. 发明授权

US06842510B2 Method of and apparatus for controlling devices 失效
标题翻译：控制装置的方法和装置
公开(公告)号：US06842510B2
公开(公告)日：2005-01-11
申请号：US10261596
申请日：2002-10-02
申请人： Mariko Sakamoto
发明人： Mariko Sakamoto
IPC分类号： G10L15/00 , G10L15/26 , G10L17/00 , H04Q9/00 , H04M11/00
CPC分类号： G10L15/26 , G10L17/00
摘要： A command detector detects a control command based on voice input through a telephone or a door phone or the like, and a user and control command identifying section identifies the user and the control command. A command controller decides execution of the control command based on a comparison between a security level set to the control command and to an authority level and a priority level set to the user.
摘要翻译：命令检测器基于通过电话或门电话等输入的语音来检测控制命令，并且用户和控制命令识别部分识别用户和控制命令。命令控制器基于设置到控制命令的安全级别与设置给用户的权限级别和优先级之间的比较来决定控制命令的执行。

3. 发明授权

US07984271B2 Processor device for out-of-order processing having reservation stations utilizing multiplexed arithmetic pipelines 有权
标题翻译：用于无序处理的处理器设备，具有利用多路复用算术流水线的保留站
公开(公告)号：US07984271B2
公开(公告)日：2011-07-19
申请号：US11875431
申请日：2007-10-19
申请人： Mariko Sakamoto , Toshio Yoshida
发明人： Mariko Sakamoto , Toshio Yoshida
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/30181 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A processor device having a reservation station (RS) is concerned. In case the processor device has plural RS, the RS is associated with an arithmetic pipeline, and two RS make a pair. When one RS of the pair cannot dispatch an instruction to an associated arithmetic pipeline, the other RS dispatches the instruction to that arithmetic pipeline, or delivers its held instruction to the one RS. In case one RS is equipped, plural entries in the RS are divided into groups, and by dynamically changing this grouping according to the dispatch frequency of the instruction to the arithmetic pipelines or the held state of the instructions, the arithmetic pipelines are efficiently utilized. Incidentally, depending on the grouping of the plural entries in the RS, a configuration as if the plural RS were allocated to each arithmetic pipeline may be realized.
摘要翻译：涉及具有保留站（RS）的处理器设备。在处理器设备具有多个RS的情况下，RS与算术流水线相关联，并且两个RS成对。当该对的一个RS不能向相关联的算术流水线发送指令时，另一个RS将指令发送到该算术流水线，或者将其保持的指令递送到一个RS。在配备一个RS的情况下，RS中的多个条目被分成组，并且通过根据指令的调度频率动态地改变该分组到算术流水线或指令的保持状态，可以有效地利用算术流水线。顺便提及，根据RS中的多个条目的分组，可以实现如同将多个RS分配给每个运算管线的配置。

4. 发明申请

US20050182611A1 Apparatus and method for simulating performance, and computer product 审中-公开
标题翻译：用于模拟性能的设备和方法，以及计算机产品
公开(公告)号：US20050182611A1
公开(公告)日：2005-08-18
申请号：US11103471
申请日：2005-04-12
申请人： Mariko Sakamoto
发明人： Mariko Sakamoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F11/3457 , G06F2201/885
摘要： A performance simulation apparatus that simulates operations of a computer, and collects and displays data that relates to dynamic conditions of hardware elements of the computer includes a graphic-data creating unit that creates graphic data for graphically displaying relationships between the dynamic conditions of the hardware elements; and a graphic-data displaying unit that displays the dynamic conditions of the hardware elements by using the graphic data that is created by the graphic-data creating unit.
摘要翻译：模拟计算机的操作并且收集和显示与计算机的硬件元件的动态条件相关的数据的性能模拟装置包括图形数据创建单元，其创建用于图形地显示硬件元件的动态条件之间的关系的图形数据 ; 以及图形数据显示单元，其通过使用由图形数据创建单元创建的图形数据来显示硬件元件的动态条件。

5. 发明授权

US06496924B2 Data processing apparatus including a plurality of pipeline processing mechanisms in which memory access instructions are carried out in a memory access pipeline 失效
标题翻译：数据处理装置包括多个流水线处理机构，其中在存储器访问管线中执行存储器访问指令
公开(公告)号：US06496924B2
公开(公告)日：2002-12-17
申请号：US09229339
申请日：1999-01-13
申请人： Mariko Sakamoto
发明人： Mariko Sakamoto
IPC分类号： G06F930
CPC分类号： G06F9/3824 , G06F9/3867 , G06F9/3885
摘要： The memory access arithmetic operation instruction is executed in the data processing apparatus including a memory access pipeline and arithmetic operation pipeline. The decoding and development of the memory access arithmetic operation are carried out after the memory access arithmetic operation instruction is input to the memory access pipeline and the memory access results and the memory access arithmetic instruction are output to the arithmetic operation pipeline.
摘要翻译：在包括存储器访问管线和算术运算管线的数据处理装置中执行存储器访问算术运算指令。存储器访问算术运算的解码和开发在存储器访问算术运算指令被输入到存储器访问管线之后进行，存储器访问结果和存储器访问算术指令被输出到算术运算管线。

6. 发明申请

US20060230237A1 Method and system for maintaining cache coherence of distributed shared memory system 审中-公开
标题翻译：用于维护分布式共享存储器系统的高速缓存一致性的方法和系统
公开(公告)号：US20060230237A1
公开(公告)日：2006-10-12
申请号：US11214850
申请日：2005-08-31
申请人： Mariko Sakamoto
发明人： Mariko Sakamoto
IPC分类号： G06F13/28
CPC分类号： G06F12/082 , G06F12/0822
摘要： A distributed shared memory system includes a plurality of nodes. Each of the nodes includes a plurality of shared multiprocessors. Each of the shared multiprocessors includes a processor, a shared cache, and a memory. Each of the nodes includes a coherence maintaining unit that maintains cache coherence based on a plurality of directories each of which corresponding to each of the shared caches included in the distributed shared memory system.
摘要翻译：分布式共享存储器系统包括多个节点。每个节点包括多个共享多处理器。每个共享多处理器包括处理器，共享缓存和存储器。每个节点包括相干维持单元，其基于多个目录来维护高速缓存一致性，每个目录对应于包括在分布式共享存储器系统中的每个共享高速缓存。

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