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1. 发明授权

US07317730B1 Queueing architecture and load balancing for parallel packet processing in communication networks 有权
标题翻译：通信网络中并行数据包处理的排队架构和负载平衡
公开(公告)号：US07317730B1
公开(公告)日：2008-01-08
申请号：US10269414
申请日：2002-10-11
申请人： Harish Devanagondi , Nicholas Bambos , Harish Belur , Richard Heaton , Majid Torabi
发明人： Harish Devanagondi , Nicholas Bambos , Harish Belur , Richard Heaton , Majid Torabi
IPC分类号： H04L12/28 , H04L12/54
CPC分类号： H04L49/9063 , H04L47/10 , H04L47/125 , H04L49/552 , H04L49/90 , H04L49/9094
摘要： A parallel packet processing queueing architecture and method are described. A packet is divided up into cells. A first or start processor queue is selected for the first cell. The following cells of the packet are then placed in the queues in a predetermined order. An example of a predetermined order is placing the cells in consecutive processor queues modulo (the number of processor queues) after the start processor. Such a predetermined order is illustrated in the context of a per Cell Contiguous Queueing (CCQ) architecture. The architecture provides benefits of alleviating the pre-processing and post-processing buffering burdens and decreasing the amount of information required for reassembly of the packet.
摘要翻译：描述并行包处理排队架构和方法。一个数据包被划分成单元格。为第一个单元选择第一个或启动处理器队列。然后将分组的以下小区以预定顺序放置在队列中。预定顺序的示例是在启动处理器之后将单元格模拟（处理器队列的数量）连续处理器队列。在每个单元连续排队（CCQ）架构的上下文中示出了这样的预定顺序。该架构提供了减轻预处理和后处理缓冲负担并减少重新组装分组所需的信息量的优点。

2. 发明授权

US07486678B1 Multi-slice network processor 有权
标题翻译：多层网络处理器
公开(公告)号：US07486678B1
公开(公告)日：2009-02-03
申请号：US10612889
申请日：2003-07-03
申请人： Harish R. Devanagondi , Harish P. Belur , Brian A. Petersen , Richard J. Heaton , Majid Torabi
发明人： Harish R. Devanagondi , Harish P. Belur , Brian A. Petersen , Richard J. Heaton , Majid Torabi
IPC分类号： H04L12/28 , H04L12/56 , H04L12/54
CPC分类号： H04L49/608 , H04L49/201 , H04L49/252 , H04L49/30 , H04L49/3009 , H04L49/3072
摘要： A multi-slice network processor processes a packet in packet slices for transfer over a multi-port network interface such as a switch fabric. The network processor segments a packet into cells having a target size. A group of cells of a common packet form a packet slice which is independently processed by one of a number of parallel processing and storage slices. Load balancing may be used in the selection of processing slices. Furthermore, the network processor may load balance slices across the multi-port network interface to one or more destination slices of another network processor. The multi-slice processor uses post header storage delivery on ingress processing to the multi-port interface thereby reducing temporary storage requirements. The multi-slice network processor may also utilize sequence numbers associated with each packet to ensure that prior to transmission onto a destination network, the packet is in the correct order for a communication flow.
摘要翻译：多层网络处理器处理分组片段中的分组以通过诸如交换结构的多端口网络接口进行传送。网络处理器将分组分割成具有目标大小的单元。公共分组的一组小区形成一个分组切片，它由多个并行处理和存储切片之一独立地处理。可以在选择处理片时使用负载平衡。此外，网络处理器可以将跨端口网络接口的平衡片段负载到另一网络处理器的一个或多个目标片段。多片处理器在多端口接口的入口处理中使用后头存储传送，从而减少临时存储要求。多层网络处理器还可以利用与每个分组相关联的序列号来确保在传输到目的地网络之前，分组对于通信流是正确的顺序。

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