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1. 发明授权

US08183886B2 Apparatus for detecting a USB host 有权
标题翻译： USB主机检测装置
公开(公告)号：US08183886B2
公开(公告)日：2012-05-22
申请号：US13023285
申请日：2011-02-08
申请人： Eric Payrat , Majid Kaabouch
发明人： Eric Payrat , Majid Kaabouch
IPC分类号： H03K19/094
CPC分类号： G06F13/385 , G06F13/4068 , Y02D10/14 , Y02D10/151
摘要： A multi-interface integrated circuit (IC) comprises a plurality of transistors, and a level detection block. At least one transistor of the plurality of transistors is in communication with a first terminal and either a first or a second lead of the multi-interface IC, and at least one of the plurality of transistors is in communication with the first terminal, a second terminal and either the first or a second lead of the multi-interface IC. The level detection block is in communication with at least one of the plurality of transistors and the first and second leads.
摘要翻译：多接口集成电路（IC）包括多个晶体管和电平检测块。所述多个晶体管中的至少一个晶体管与所述多接口IC的第一端子和第一或第二引线连通，并且所述多个晶体管中的至少一个晶体管与所述第一端子通信，第二端子和多接口IC的第一或第二引线。电平检测块与多个晶体管和第一和第二引线中的至少一个通信。

2. 发明申请

US20100037000A1 ONE-TIME-PROGRAMMABLE MEMORY EMULATION 有权
标题翻译：一次可编程存储器仿真
公开(公告)号：US20100037000A1
公开(公告)日：2010-02-11
申请号：US12185932
申请日：2008-08-05
申请人： Majid Kaabouch , Carine Lefort , Jean-Pascal Maraninchi
发明人： Majid Kaabouch , Carine Lefort , Jean-Pascal Maraninchi
IPC分类号： G06F12/02
CPC分类号： G11C7/24 , G11C16/102 , G11C16/22
摘要： This document discloses one-time-programmable (“OTP”) memory emulation and methods of performing the same. OTP memory can be emulated by managing reads and writes to a memory array in response to an instruction to write data to a OTP memory location and selectively setting a security flag that corresponds to the memory locations. The memory array can be a NAND Flash memory array that includes multiple pages of memory. The memory array can be defined by memory blocks that can include multiple pages of memory. When an OTP write instruction is received, previously stored data can be read from a first page of memory, combined with the new data and stored to a target page of memory. A security flag can be set to prevent the target page from being reprogrammed prior to an erase.
摘要翻译：本文件公开了一次可编程（“OTP”）存储器仿真及其执行方法。 OTP存储器可以通过管理对存储器阵列的读取和写入来响应于向OTP存储器位置写入数据的指令并且选择性地设置对应于存储器位置的安全标志来仿真。存储器阵列可以是包括多页存储器的NAND闪存阵列。存储器阵列可以由可以包括多页存储器的存储器块来定义。当接收到OTP写指令时，可以从存储器的第一页读取先前存储的数据，并与新数据组合并存储到存储器的目标页面。可以设置安全标志以防止在擦除之前对目标页进行重新编程。

3. 发明授权

US08782433B2 Data security 有权
标题翻译：数据安全
公开(公告)号：US08782433B2
公开(公告)日：2014-07-15
申请号：US12207983
申请日：2008-09-10
申请人： Majid Kaabouch , Alexandre Croguennec , Carine Lefort
发明人： Majid Kaabouch , Alexandre Croguennec , Carine Lefort
IPC分类号： G06F12/14 , G06F21/85
CPC分类号： G06F21/85 , G06F12/1408
摘要： This document discloses data security systems and methods of securing data. A cache memory can be connected between a decryption engine and a central processing unit (“CPU”) to increase security of encrypted data that is stored in a datastore. The decryption engine can retrieve the encrypted data from the datastore, decrypt the data, and store the decrypted data in the cache. In turn, the decrypted data can be accessed by the CPU. The data can be encrypted with a secret key, so that decryption can be performed with the secret key. The key can be varied based on a memory address associated with the data. The key can be protected by restricting direct access to the decryption engine by the CPU.
摘要翻译：本文件公开了数据安全系统和数据保护方法。缓存存储器可以连接在解密引擎和中央处理单元（“CPU”）之间，以增加存储在数据存储区中的加密数据的安全性。解密引擎可以从数据存储区检索加密的数据，解密数据，并将解密的数据存储在缓存中。反过来，解密的数据可以被CPU访问。可以使用秘密密钥对数据进行加密，从而可以用密钥执行解密。密钥可以根据与数据相关联的存储器地址而变化。可以通过限制CPU直接访问解密引擎来保护密钥。

4. 发明申请

US20090150681A1 Secure Software Download 有权
标题翻译：安全软件下载
公开(公告)号：US20090150681A1
公开(公告)日：2009-06-11
申请号：US11952880
申请日：2007-12-07
申请人： Majid Kaabouch , Alexandre Croguennec , Eric Le Cocquen
发明人： Majid Kaabouch , Alexandre Croguennec , Eric Le Cocquen
IPC分类号： G06F12/14
CPC分类号： H04L9/14 , H04L2209/60 , H04L2209/80
摘要： Software can be downloaded securely using a multi-encryption method, where the decryption is completed when the software is executed. In one aspect, a multi-encrypted data item is received. One or more of the encryptions on the multi-encrypted data item is decrypted, yielding a partially decrypted data item. The partially decrypted data item is stored in a reserved portion of a storage medium. The partially decrypted data item is fetched from the storage medium and decrypted to yield the data item. The decryption can be performed using one or more circuits that implement multiple decryption processes, including multiple algorithm-key combinations.
摘要翻译：可以使用多加密方式安全地下载软件，在执行软件时解密完成。在一个方面，接收多加密数据项。解密多加密数据项上的一个或多个加密，产生部分解密的数据项。部分解密的数据项存储在存储介质的保留部分中。部分解密的数据项从存储介质中取出并被解密以产生数据项。可以使用实现多个解密过程的一个或多个电路来执行解密，包括多个算法 - 密钥组合。

5. 发明申请

US20080040593A1 EMBEDDED SOFTWARE CAMOUFLAGE AGAINST CODE REVERSE ENGINEERING 有权
标题翻译：嵌入式软件防范代码反向工程
公开(公告)号：US20080040593A1
公开(公告)日：2008-02-14
申请号：US11558357
申请日：2006-11-09
申请人： Majid Kaabouch , Eric Le Cocquen
发明人： Majid Kaabouch , Eric Le Cocquen
IPC分类号： G06F7/38
CPC分类号： G06F21/77 , G06F21/52 , G06F21/75 , G06F21/755
摘要： Methods and apparatus for identifying a first flow control instruction in an executing program, the first instruction being associated with a first program address at which program execution will continue after execution of the first instruction. A determination is made as to whether the first program address is protected. If the first program address is protected, a first alternate program address is substituted for the first program address such that program execution will continue at the first alternate program address after execution of the first instruction.
摘要翻译：用于识别执行程序中的第一流控制指令的方法和装置，所述第一指令与执行所述第一指令之后程序执行将继续的第一程序地址相关联。确定第一个程序地址是否受到保护。如果第一程序地址被保护，则第一替代程序地址被替换为第一程序地址，使得在执行第一指令之后程序执行将在第一备用程序地址处继续。

6. 发明授权

US07906989B2 Apparatus for detecting a USB host 有权
标题翻译： USB主机检测装置
公开(公告)号：US07906989B2
公开(公告)日：2011-03-15
申请号：US12051935
申请日：2008-03-20
申请人： Eric Payrat , Majid Kaabouch
发明人： Eric Payrat , Majid Kaabouch
IPC分类号： H03K19/094
CPC分类号： G06F13/385 , G06F13/4068 , Y02D10/14 , Y02D10/151
摘要： A multi-interface integrated circuit (IC) comprises a plurality of transistors, and a level detection block. At least one transistor of the plurality of transistors is in communication with a first terminal and either a first or a second lead of the multi-interface IC, and at least one of the plurality of transistors is in communication with the first terminal, a second terminal and either the first or a second lead of the multi-interface IC. The level detection block is in communication with at least one of the plurality of transistors and the first and second leads.
摘要翻译：多接口集成电路（IC）包括多个晶体管和电平检测块。所述多个晶体管中的至少一个晶体管与所述多接口IC的第一端子和第一或第二引线连通，并且所述多个晶体管中的至少一个晶体管与所述第一端子通信，第二端子和多接口IC的第一或第二引线。电平检测块与多个晶体管和第一和第二引线中的至少一个通信。

7. 发明申请

US20080072051A1 BI-PROCESSOR ARCHITECTURE FOR SECURE SYSTEMS 有权
标题翻译：用于安全系统的BI处理器架构
公开(公告)号：US20080072051A1
公开(公告)日：2008-03-20
申请号：US11558367
申请日：2006-11-09
申请人： Majid Kaabouch , Eric Le Cocquen
发明人： Majid Kaabouch , Eric Le Cocquen
IPC分类号： H04L9/00
CPC分类号： G06F21/556 , G06F21/74 , G06F21/75 , G06F21/77
摘要： Systems, methods and program products for a first central processing unit (CPU) configured to perform tasks that do not require manipulation of sensitive information and a second CPU that is configured to perform tasks that manipulate the sensitive information on behalf of the first CPU. The first CPU and the second CPU can communicate through a secure interface. The first CPU cannot access the sensitive information within the second CPU.
摘要翻译：被配置为执行不需要操纵敏感信息的任务的第一中央处理单元（CPU）的系统，方法和程序产品以及被配置为执行代表第一CPU操纵敏感信息的任务的第二CPU。第一个CPU和第二个CPU可以通过安全的界面进行通信。第一个CPU无法访问第二个CPU中的敏感信息。

8. 发明申请

US20070260861A1 Method and system for controlling timing in a processor 有权
标题翻译：用于控制处理器中的定时的方法和系统
公开(公告)号：US20070260861A1
公开(公告)日：2007-11-08
申请号：US11416651
申请日：2006-05-02
申请人： Majid Kaabouch , Eric Cocquen
发明人： Majid Kaabouch , Eric Cocquen
IPC分类号： G06F9/44
CPC分类号： G06F9/3836 , G06F9/30058 , G06F9/30069 , G06F9/30181 , G06F9/30189 , G06F9/325 , G06F9/3869 , G06F21/75
摘要： A method and system for controlling timing in a processor. In one aspect of the present invention, the method comprises fetching a plurality of instructions, wherein each instruction has a first default execution time during a first condition, and wherein each instruction has a second default execution time during a second condition; during a first mode, executing the plurality of instructions within a same execution time regardless of whether a condition is the first condition or the second condition; and during a second mode, executing the plurality of instructions within random execution time regardless of whether a condition is the first condition or the second condition. According to the system and method disclosed herein, the method effectively modifies the timing of a processor by controlling and/or minimizing variations in the execution times of instructions.
摘要翻译：一种用于控制处理器中的定时的方法和系统。在本发明的一个方面，所述方法包括获取多个指令，其中每个指令在第一条件期间具有第一默认执行时间，并且其中每个指令在第二条件期间具有第二默认执行时间; 在第一模式期间，无论条件是第一条件还是第二条件，在相同的执行时间内执行多个指令; 并且在第二模式期间，无论条件是第一条件还是第二条件，都在随机执行时间内执行多个指令。根据本文公开的系统和方法，该方法通过控制和/或最小化指令的执行时间的变化来有效地修改处理器的定时。

9. 发明授权

US08213612B2 Secure software download 有权
标题翻译：安全软件下载
公开(公告)号：US08213612B2
公开(公告)日：2012-07-03
申请号：US11952880
申请日：2007-12-07
申请人： Majid Kaabouch , Alexandre Croguennec , Eric Le Cocquen
发明人： Majid Kaabouch , Alexandre Croguennec , Eric Le Cocquen
IPC分类号： G06F21/00 , G06F11/30 , G06F12/14 , H04L9/00
CPC分类号： H04L9/14 , H04L2209/60 , H04L2209/80
摘要： Software can be downloaded securely using a multi-encryption method, where the decryption is completed when the software is executed. In one aspect, a multi-encrypted data item is received. One or more of the encryptions on the multi-encrypted data item is decrypted, yielding a partially decrypted data item. The partially decrypted data item is stored in a reserved portion of a storage medium. The partially decrypted data item is fetched from the storage medium and decrypted to yield the data item. The decryption can be performed using one or more circuits that implement multiple decryption processes, including multiple algorithm-key combinations.
摘要翻译：可以使用多加密方式安全地下载软件，在执行软件时解密完成。在一个方面，接收多加密数据项。解密多加密数据项上的一个或多个加密，产生部分解密的数据项。部分解密的数据项存储在存储介质的保留部分中。部分解密的数据项从存储介质中取出并被解密以产生数据项。可以使用实现多个解密过程的一个或多个电路来执行解密，包括多个算法 - 密钥组合。

10. 发明授权

US07774587B2 Dynamic redundancy checker against fault injection 有权
标题翻译：动态冗余校验器防止故障注入
公开(公告)号：US07774587B2
公开(公告)日：2010-08-10
申请号：US11486232
申请日：2006-07-12
申请人： Majid Kaabouch , Yves Fusella , Laurent Paris
发明人： Majid Kaabouch , Yves Fusella , Laurent Paris
IPC分类号： G06F9/00
CPC分类号： G06F11/1008 , G06F21/52 , G11C2029/0409
摘要： A method and system for checking data stored in a memory of in a computer system is disclosed. The memory includes a plurality of memory addresses. The method and system include providing a signature generator coupled with the memory, providing a checker memory coupled with the signature generator and separate from the memory, and providing an address remapper coupled with the checker memory and the memory. The signature generator provides at least one signature corresponding to the data, which resides in a protection window of the memory. The protection window includes at least one memory address of the plurality of memory addresses. The checker memory stores the at least one signature in at least one checker address, which corresponds to the at least one memory address. The address remapper for translates between the at least one memory address and the at least one checker address.
摘要翻译：公开了一种用于检查存储在计算机系统中的存储器中的数据的方法和系统。存储器包括多个存储器地址。所述方法和系统包括提供与存储器耦合的签名生成器，提供与签名生成器耦合并与存储器分离的检查器存储器，以及提供与检验器存储器和存储器耦合的地址重映射器。签名生成器提供与数据相对应的至少一个签名，驻留在存储器的保护窗口中。保护窗口包括多个存储器地址的至少一个存储器地址。检查器存储器将至少一个签名存储在对应于至少一个存储器地址的至少一个检查器地址中。所述地址重映射器用于在所述至少一个存储器地址和所述至少一个检验器地址之间进行转换。

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