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1. 发明授权

US07412213B1 Envelope limiting for polar modulators 有权
标题翻译：极性调制器的信封限制
公开(公告)号：US07412213B1
公开(公告)日：2008-08-12
申请号：US11538396
申请日：2006-10-03
申请人： John B. Groe , Carl Thomas Hardin , Mahbuba Sheba
发明人： John B. Groe , Carl Thomas Hardin , Mahbuba Sheba
IPC分类号： H04B1/02 , H03C3/38
CPC分类号： H03G7/06 , H03C5/00 , H03F1/02 , H03F3/24 , H03G3/3042 , H04B2001/0408 , H04B2001/045 , H04L27/361
摘要： Envelope limiting for a polar modulator. A system is provided that intelligently compresses the amplitude modulation in a polar modulator so that it can be implemented with a single-stage variable gain amplifier. Limiting the amplitude modulation range on the low side prevents collapse of the transmit signal's time-varying envelope and eases circuit implementation. Limiting the amplitude modulation range on the high side reduces the peak-to-average ratio of the waveform and thereby improves the efficiency of the radio transmitter.
摘要翻译：极性调制器的信封限制。提供了一种智能地压缩极性调制器中的幅度调制的系统，使得其可以用单级可变增益放大器来实现。限制低侧的幅度调制范围可以防止发射信号的时变包络的崩溃，并且简化电路实现。限制高侧的幅度调制范围降低了波形的峰均比，从而提高了无线电发射机的效率。

2. 发明授权

US07786913B2 Digital phase locked loop with dithering 有权
标题翻译：数字锁相环与抖动
公开(公告)号：US07786913B2
公开(公告)日：2010-08-31
申请号：US12114726
申请日：2008-05-02
申请人： Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
发明人： Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
IPC分类号： H03M3/00
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。抖动电路耦合到参考信号，并将短序列抖动信号注入到参考信号中，以便克服量化噪声，从而改进整数信道的RMS相位误差检测。

3. 发明申请

US20080315928A1 DIGITAL PHASE LOCKED LOOP WITH DITHERING 有权
标题翻译：数字相位锁定环
公开(公告)号：US20080315928A1
公开(公告)日：2008-12-25
申请号：US12114726
申请日：2008-05-02
申请人： Khurram WAHEED , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
发明人： Khurram WAHEED , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
IPC分类号： H03L7/06 , H03M1/20
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。抖动电路耦合到参考信号，并将短序列抖动信号注入到参考信号中，以便克服量化噪声，从而改进整数信道的RMS相位误差检测。

4. 发明授权

US07171170B2 Envelope limiting for polar modulators 有权
标题翻译：极性调制器的信封限制
公开(公告)号：US07171170B2
公开(公告)日：2007-01-30
申请号：US10202501
申请日：2002-07-23
申请人： John B. Groe , Carl Thomas Hardin , Mahbuba Sheba
发明人： John B. Groe , Carl Thomas Hardin , Mahbuba Sheba
IPC分类号： H04B1/02 , H03C3/38
CPC分类号： H03G7/06 , H03C5/00 , H03F1/02 , H03F3/24 , H03G3/3042 , H04B2001/0408 , H04B2001/045 , H04L27/361
摘要： Envelope limiting for a polar modulator. A system is provided that intelligently compresses the amplitude modulation in a polar modulator so that it can be implemented with a single-stage variable gain amplifier. Limiting the amplitude modulation range on the low side prevents collapse of the transmit signal's time-varying envelope and eases circuit implementation. Limiting the amplitude modulation range on the high side reduces the peak-to-average ratio of the waveform and thereby improves the efficiency of the radio transmitter.
摘要翻译：极性调制器的信封限制。提供了一种智能地压缩极性调制器中的幅度调制的系统，使得其可以用单级可变增益放大器来实现。限制低侧的幅度调制范围可以防止发射信号的时变包络的崩溃，并且简化电路实现。限制高侧的幅度调制范围降低了波形的峰均比，从而提高了无线电发射机的效率。

5. 发明授权

US07920081B2 Digital phase locked loop with dithering 有权
标题翻译：数字锁相环与抖动
公开(公告)号：US07920081B2
公开(公告)日：2011-04-05
申请号：US12841354
申请日：2010-07-22
申请人： Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
发明人： Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
IPC分类号： H03M1/06
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。抖动电路耦合到参考信号，并将短序列抖动信号注入到参考信号中，以便克服量化噪声，从而改进整数信道的RMS相位误差检测。

6. 发明申请

US20100283654A1 DIGITAL PHASE LOCKED LOOP WITH DITHERING 有权
标题翻译：数字相位锁定环
公开(公告)号：US20100283654A1
公开(公告)日：2010-11-11
申请号：US12841354
申请日：2010-07-22
申请人： Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
发明人： Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
IPC分类号： H03M1/50 , H03M1/12
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。抖动电路耦合到参考信号，并将短序列抖动信号注入到参考信号中，以便克服量化噪声，从而改进整数信道的RMS相位误差检测。

7. 发明申请

US20110148676A1 DIGITAL PHASE LOCKED LOOP WITH DITHERING 审中-公开
标题翻译：数字相位锁定环
公开(公告)号：US20110148676A1
公开(公告)日：2011-06-23
申请号：US13038885
申请日：2011-03-02
申请人： Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
发明人： Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
IPC分类号： H03M1/20
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。抖动电路耦合到参考信号，并将短序列抖动信号注入到参考信号中，以便克服量化噪声，从而改进整数信道的RMS相位误差检测。

8. 发明授权

US06301311B1 Non-coherent, non-data-aided pseudo-noise synchronization and carrier synchronization for QPSK or OQPSK modulated CDMA system 失效
标题翻译：用于QPSK或OQPSK调制CDMA系统的非相干，非数据辅助伪噪声同步和载波同步
公开(公告)号：US06301311B1
公开(公告)日：2001-10-09
申请号：US09247425
申请日：1999-02-10
申请人： Mahbuba Sheba
发明人： Mahbuba Sheba
IPC分类号： H04L7027
CPC分类号： H04B1/70775 , H04B1/70718 , H04B1/7075 , H04B1/7087 , H04B2001/70706 , H04L27/2273
摘要： A non-coherent method for (PN) code synchronization and eliminates the need for prior clock synchronization between a transmitter and receiver. The method further eliminates any need for prior knowledge of a transmitted data sequence to provide synchronization. In the method, based on a coarse estimation of the carrier frequency, a received CDMA intermediate frequency (IF) signal is baseband converted to in-phase (I) and quadrature-phase (Q) components. The baseband I and Q components are then used to calculate an estimated delay {circumflex over (&tgr;)} at a PN synchronization roll-over point. The estimated delay {circumflex over (&tgr;)} is used in an intermediate data sequence in the synchronization roll-over calculation process to more accurately estimate carrier frequency error and phase offset for the IF carrier signal used in the baseband conversion process. The estimated carrier signal is then provided as feed back to correct for the coarse estimate of the carrier frequency error and phase offset, thus adaptively correcting for Doppler shift in a received signal.
摘要翻译：一种用于（PN）码同步的非相干方法，不需要发射机和接收机之间的以前的时钟同步。该方法进一步消除了对发送的数据序列的先验知识的任何需要以提供同步。在该方法中，基于载波频率的粗略估计，接收的CDMA中频（IF）信号被基带转换为同相（I）和正交相（Q）分量。然后，基带I和Q分量用于计算PN同步翻转点处的估计延迟（在（＆tgr））上的回波。在同步翻转计算过程中，在中间数据序列中使用估计的延迟（（＆tgr））}，以更准确地估计用于基带转换处理中的IF载波信号的载波频率误差和相位偏移。然后提供估计的载波信号作为反馈以校正载波频率误差和相位偏移的粗略估计，从而自适应地校正接收信号中的多普勒频移。

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