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1. 发明授权

US08687455B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08687455B2
公开(公告)日：2014-04-01
申请号：US13205900
申请日：2011-08-09
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
IPC分类号： G11C8/00
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译：通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。

2. 发明授权

US07924615B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07924615B2
公开(公告)日：2011-04-12
申请号：US12714750
申请日：2010-03-01
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
IPC分类号： G11C11/34
CPC分类号： G11C16/3436
摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.
摘要翻译：非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

3. 发明授权

US07515479B2 Nonvolatile semiconductor storage device and method for writing therein 有权
标题翻译：非易失性半导体存储装置及其写入方法
公开(公告)号：US07515479B2
公开(公告)日：2009-04-07
申请号：US10598853
申请日：2005-11-01
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
IPC分类号： G11C11/34
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and bit data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译：通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行位数据写入。当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。

4. 发明申请

US20080019162A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 审中-公开
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20080019162A1
公开(公告)日：2008-01-24
申请号：US11758108
申请日：2007-06-05
申请人： Taku OGURA , Masaaki Mihara , Yoshiki Kawajiri
发明人： Taku OGURA , Masaaki Mihara , Yoshiki Kawajiri
IPC分类号： G11C5/06
CPC分类号： G11C11/412 , G11C14/00 , G11C14/0063
摘要： This non-volatile semiconductor storage device includes a flip-flop in which two inverters, each consisting of a load transistor and a storage transistor connected in series, are cross-connected; and two gate transistors, each respectively connected to a node of the flip-flop on a side thereof. The storage transistors of the inverters are constituted by storage transistors which can be threshold voltage controlled by injection of electrons into the neighborhood of their gates. This non-volatile semiconductor storage device further includes two bit lines, each of which is connected to a respective one of the two gate transistors; a word line which is connected to both of the gate electrodes of the two gate transistors; a first voltage supply line which is connected to the sources of the storage transistors of the inverters; and a second voltage supply line which is connected to the sources of the load transistors of the inverters.
摘要翻译：这种非易失性半导体存储器件包括一个触发器，其中每个由串联连接的负载晶体管和存储晶体管组成的两个反相器是交叉连接的; 以及两个栅极晶体管，每个分别在触发器的一侧分别连接到触发器的节点。反相器的存储晶体管由存储晶体管构成，其可以通过将电子注入其栅极附近来控制阈值电压。该非易失性半导体存储装置还包括两个位线，每个位线连接到两个栅极晶体管中的相应一个; 连接到两个栅极晶体管的两个栅电极的字线; 连接到逆变器的存储晶体管的源极的第一电源线; 以及与逆变器的负载晶体管的源极连接的第二电压供给线。

5. 发明授权

US07274176B2 Regulator circuit having a low quiescent current and leakage current protection 有权
标题翻译：稳压电路具有低静态电流和漏电流保护
公开(公告)号：US07274176B2
公开(公告)日：2007-09-25
申请号：US10999358
申请日：2004-11-29
申请人： Masaaki Mihara
发明人： Masaaki Mihara
IPC分类号： G05F1/59
CPC分类号： G05F1/575
摘要： A voltage regulator includes first and second transistors arranged in parallel and configured to regulate current flow to an output node, and a sensing circuit configured to sense a voltage level at the output node and provide a signal proportional thereto. the regulator also includes a control circuit configured to receive the signal from the sensing circuit and provide control signals at control terminals of the first and second transistors such that voltage at the output node is maintained substantially at a selected level. The control circuit further configured to hold the second transistor in an off state while a demand for current at the output node remains below an output threshold. The second transistor is configured to control a large portion of load current above the output threshold. The regulator may also include a current bypass circuit configured to shunt leakage current of the second transistor to ground, away from the sensing circuit.
摘要翻译：电压调节器包括并联布置并被配置成调节到输出节点的电流的第一和第二晶体管，以及被配置为感测输出节点处的电压电平并提供与其成比例的信号的感测电路。调节器还包括控制电路，其被配置为从感测电路接收信号，并在第一和第二晶体管的控制端提供控制信号，使得输出节点处的电压基本维持在选定的电平。所述控制电路还被配置为将所述第二晶体管保持在断开状态，同时对所述输出节点处的电流的需求保持在输出阈值以下。第二晶体管被配置为控制大于输出阈值的大部分负载电流。调节器还可以包括电流旁路电路，其配置成将第二晶体管的漏电流分流到接地，远离感测电路。

6. 发明授权

US06788577B2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US06788577B2
公开(公告)日：2004-09-07
申请号：US10188082
申请日：2002-07-03
申请人： Masaaki Mihara
发明人： Masaaki Mihara
IPC分类号： G11C1604
CPC分类号： G11C8/08 , G11C16/08 , G11C16/28
摘要： A nonvolatile semiconductor memory which is provided with a plurality of memory elements each having a control gate and a floating gate such that data is stored by electron injection to the floating gate and electron emission from the floating gate, including an electric current detecting circuit for detecting a drain current supplied to a drain of each of the memory elements and a voltage control circuit for controlling a gate voltage supplied to the control gate of each of the memory elements, in accordance with the drain current detected by the electric current detecting circuit.
摘要翻译：一种非易失性半导体存储器，其具有多个存储元件，每个存储元件具有控制栅极和浮置栅极，使得通过电子注入存储浮动栅极的数据和来自浮置栅极的电子发射，包括用于检测的电流检测电路提供给每个存储元件的漏极的漏极电流和用于根据由电流检测电路检测的漏极电流来控制提供给每个存储元件的控制栅极的栅极电压的电压控制电路。

7. 发明授权

US06735119B2 Nonvolatile semiconductor memory 失效
公开(公告)号：US06735119B2
公开(公告)日：2004-05-11
申请号：US10338635
申请日：2003-01-09
申请人： Masaaki Mihara
发明人： Masaaki Mihara
IPC分类号： G11C1604
CPC分类号： G11C16/30
摘要： In a nonvolatile semiconductor memory provided with a plurality of memory elements each having a control gate and a floating gate, an electric current detecting circuit detects a drain current supplied to a drain of each of the memory elements and a voltage control circuit controls, in accordance with the drain current detected by the electric current detecting circuit, a control gate voltage supplied to the control gate of each of the memory elements.

8. 发明授权

US06560164B2 Semiconductor integrated circuit device with internal clock generating circuit 失效
公开(公告)号：US06560164B2
公开(公告)日：2003-05-06
申请号：US09977275
申请日：2001-10-16
申请人： Shinji Kawai , Masaaki Mihara
发明人： Shinji Kawai , Masaaki Mihara
IPC分类号： G11C800
CPC分类号： H03L1/027 , G11C5/145 , G11C5/147 , G11C16/32 , H03L1/022
摘要： A temperature dependency of an internal clock signal generated by an internal clock generating circuit is effectively reduced. A temperature detecting circuit is provided to a variable clock generator for generating the internal clock signal and an oscillating cycle period of the variable clock generator is altered according to a detection signal of the temperature detecting circuit. A cycle of the internal clock signal is altered and a temperature dependency of the internal clock signal is effectively compensated for.

9. 发明授权

US06385086B1 Nonvolatile semiconductor memory device capable of high speed generation of rewrite voltage 失效
标题翻译：能够高速产生重写电压的非易失性半导体存储器件
公开(公告)号：US06385086B1
公开(公告)日：2002-05-07
申请号：US09735618
申请日：2000-12-14
申请人： Masaaki Mihara , Yoshikazu Miyawaki , Shinji Kawai
发明人： Masaaki Mihara , Yoshikazu Miyawaki , Shinji Kawai
IPC分类号： G11C1604
CPC分类号： G11C16/12 , G11C5/147 , G11C16/30
摘要： A voltage generation portion includes a voltage amplifier circuit, receiving a boosted potential VPP generated by a charge pump circuit to output an output potential Vout equal to a standard potential VIN. Output potentials Vout are distributed as voltages for rewriting and erasing on a flash memory via distributor. The output potential Vout can be changed faster than the boosted potential VPP generated by the charge pump circuit does.
摘要翻译：电压产生部分包括电压放大器电路，接收由电荷泵电路产生的升压电位VPP，以输出等于标准电位VIN的输出电位Vout。输出电位Vout分配为经由分配器在闪速存储器上重写和擦除的电压。输出电位Vout可以比由电荷泵电路产生的升压电位VPP更快地改变。

10. 发明授权

US06180996B2 Semiconductor device comprising a polydiode element 失效
标题翻译：包括多晶硅元件的半导体器件
公开(公告)号：US06180996B2
公开(公告)日：2001-01-30
申请号：US09115518
申请日：1998-07-15
申请人： Hiroshi Onoda , Masaaki Mihara , Hiroshi Takada
发明人： Hiroshi Onoda , Masaaki Mihara , Hiroshi Takada
IPC分类号： H01L2900
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11546
摘要： An aluminum wire is connected to a P-type layer of a polydiode element through a resistive element consisting of a barrier metal film and a tungsten plug. Another aluminum wire is connected to an N-type layer of the polydiode element through another resistive element consisting of another barrier metal film and another tungsten plug. Thus, a semiconductor device including a polydiode element which is resistant to surge or contamination is provided.
摘要翻译：铝线通过由阻挡金属膜和钨插塞构成的电阻元件连接到多晶硅元件的P型层。另一铝线通过由另一个阻挡金属膜和另一个钨插塞组成的另一个电阻元件连接到多晶硅元件的N型层。因此，提供了一种包括抗电涌或污染的多极体元件的半导体器件。

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