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1. 发明授权

US09042173B2 Efficient memory sense architecture 有权
标题翻译：高效的内存感觉架构
公开(公告)号：US09042173B2
公开(公告)日：2015-05-26
申请号：US12696766
申请日：2010-01-29
申请人： Harvey J. Stiegler , Luan A. Dang
发明人： Harvey J. Stiegler , Luan A. Dang
IPC分类号： G11C16/04 , G11C16/06 , G11C7/02
CPC分类号： G11C7/02 , G11C16/04 , G11C16/06
摘要： Memory architecture, such as for a flash EEPROM memory embedded within a processor or other large scale integrated circuit, and including differential sense circuitry. The memory includes an array of memory cells in rows and columns, and organized into sectors, each sector split into portions. Columns of the array are grouped into small groups from which a final stage column decode selects a column from the group based on the least significant bits of the column address. Adjacent groups of columns are paired, with a selected column from each group coupled to a differential input of the sense amplifier, but with one of the selected columns associated with an unselected sector portion and thus serving as a dummy bit line. Conductor routing is simplified, and chip area is reduced, by maintaining unselected column groups adjacent or nearby to selected column groups.
摘要翻译：存储架构，例如嵌入在处理器或其他大规模集成电路内的闪存EEPROM存储器，并且包括差分感测电路。存储器包括行和列中的存储器单元阵列，并且被组织成扇区，每个扇区被分割成部分。阵列的列被分组成小组，最后一列列解码根据列地址的最低有效位从组中选择一列。列的相邻组被配对，其中来自每个组的选定的列耦合到读出放大器的差分输入，但是其中一个所选列与未选择的扇区部分相关联，并且因此用作虚拟位线。通过将未选择的列组保持在选定的列组相邻或附近，导体布线简化，并减少了芯片面积。

2. 发明申请

US20110188311A1 Efficient Memory Sense Architecture 有权
标题翻译：高效的内存感知架构
公开(公告)号：US20110188311A1
公开(公告)日：2011-08-04
申请号：US12696766
申请日：2010-01-29
申请人： Harvey J. Stiegler , Luan A. Dang
发明人： Harvey J. Stiegler , Luan A. Dang
IPC分类号： G11C16/04 , G11C16/06 , G11C7/02
CPC分类号： G11C7/02 , G11C16/04 , G11C16/06
摘要： Memory architecture, such as for a flash EEPROM memory embedded within a processor or other large scale integrated circuit, and including differential sense circuitry. The memory includes an array of memory cells in rows and columns, and organized into sectors, each sector split into portions. Columns of the array are grouped into small groups from which a final stage column decode selects a column from the group based on the least significant bits of the column address. Adjacent groups of columns are paired, with a selected column from each group coupled to a differential input of the sense amplifier, but with one of the selected columns associated with an unselected sector portion and thus serving as a dummy bit line. Conductor routing is simplified, and chip area is reduced, by maintaining unselected column groups adjacent or nearby to selected column groups.
摘要翻译：存储架构，例如嵌入在处理器或其他大规模集成电路内的闪存EEPROM存储器，并且包括差分感测电路。存储器包括行和列中的存储器单元阵列，并且被组织成扇区，每个扇区被分割成部分。阵列的列被分组成小组，最后一列列解码根据列地址的最低有效位从组中选择一列。列的相邻组被配对，其中来自每个组的选定的列耦合到读出放大器的差分输入，但是其中一个所选列与未选择的扇区部分相关联，并且因此用作虚拟位线。通过将未选择的列组保持在选定的列组相邻或附近，导体布线简化，并减少了芯片面积。

3. 发明授权

US07489584B2 High performance, low-leakage static random access memory (SRAM) 有权
标题翻译：高性能，低泄漏静态随机存取存储器（SRAM）
公开(公告)号：US07489584B2
公开(公告)日：2009-02-10
申请号：US11126644
申请日：2005-05-11
申请人： Luan A. Dang , Hiep Van Tran
发明人： Luan A. Dang , Hiep Van Tran
IPC分类号： G11C8/00
CPC分类号： G11C11/417 , G11C8/08
摘要： Systems and methods are provided for reducing leakage current and maintaining high performance in a static random access memory (SRAM). One embodiment discloses a memory array system operative to store data bits in individually addressable rows and columns. The memory array system comprises a plurality of memory blocks, each of the plurality of memory blocks having a plurality of memory rows and a row peripheral circuit operative to switch a memory block from a retention mode to an activation mode in response to an addressing of a memory row within the memory block.
摘要翻译：提供了系统和方法来减少泄漏电流并保持静态随机存取存储器（SRAM）中的高性能。一个实施例公开了一种可操作地将数据位存储在可单独寻址的行和列中的存储器阵列系统。所述存储器阵列系统包括多个存储块，所述多个存储器块中的每一个具有多个存储器行，以及行外围电路，用于响应于所述存储器块的寻址而将存储块从保持模式切换到激活模式内存块内的内存行。

4. 发明授权

US06956398B1 Leakage current reduction method 有权
标题翻译：泄漏电流还原法
公开(公告)号：US06956398B1
公开(公告)日：2005-10-18
申请号：US10806624
申请日：2004-03-23
申请人： Hugh Mair , Luan A. Dang , Xiaowei Deng , George B. Jamison , Tam M. Tran , Shyh-Horng Yang , David B. Scott
发明人： Hugh Mair , Luan A. Dang , Xiaowei Deng , George B. Jamison , Tam M. Tran , Shyh-Horng Yang , David B. Scott
IPC分类号： H03K17/16 , H03K19/00 , H03K19/003
CPC分类号： H03K19/00361 , H03K19/0016
摘要： The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.
摘要翻译：用于为数据保持模式断电的方法包括：将电源电压节点从有功功率电压电平改变为无功功率电平; 将P沟道器件的源极耦合到电源电压节点; 向P通道装置的后门提供保持电源电压电平; 将P沟道器件的漏极电压改变到参考电压电平，其中所述参考电压电平不同于所述保持电源电压电平; 并将P沟道器件的栅极电压改变到参考电压电平。

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