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1. 发明授权

US5926433A Dual strobed negative pumped worldlines for dynamic random access memories 失效
标题翻译：用于动态随机存取存储器的双选通负抽吸世界线
公开(公告)号：US5926433A
公开(公告)日：1999-07-20
申请号：US806703
申请日：1997-01-29
申请人： Loren L. McLaury
发明人： Loren L. McLaury
IPC分类号： G11C8/08 , G11C11/408 , G11C13/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： The invention is a circuit and a method for resetting a wordline by driving a potential of the wordline toward a ground reference potential prior to driving the potential of the wordline to a negative potential.
摘要翻译：本发明是一种电路和方法，用于在将字线的电位驱动到负电位之前通过将字线的电位驱动到接地参考电位来重置字线。

2. 发明授权

US5325502A Pipelined SAM register serial output 失效
标题翻译：流水线SAM寄存器串行输出
公开(公告)号：US5325502A
公开(公告)日：1994-06-28
申请号：US701470
申请日：1991-05-15
申请人： Loren L. McLaury
发明人： Loren L. McLaury
IPC分类号： G11C7/10 , G06F9/32
CPC分类号： G11C7/1075
摘要： Serial clock cycle time for a serial read operation in a semiconductor memory is reduced by partitioning the read operation into a sensing operation, a counter operation and an output operation, and conducting all three operations simultaneously in a pipelined fashion. To carry out the new method, the memory effectively is pipelined by providing a read register (92) between the sensing flip-flop (90) and the output latch/driver (96), and by isolating the address counter (48) from the address decoder circuitry (56) by inserting an isolation buffer (52). Additionally, the serial access time is reduced by conducting a look-ahead load (72) of a first tap address at the conclusion of a read transfer cycle, without waiting for the serial clock signal (SC) to begin the read cycle.
摘要翻译：通过将读取操作划分为感测操作，计数器操作和输出操作以及以流水线方式同时进行所有三个操作来减少用于半导体存储器中的串行读取操作的串行时钟周期时间。为了执行新方法，通过在感测触发器（90）和输出锁存器/驱动器（96）之间提供读取寄存器（92）来有效地存储存储器，并且通过将地址计数器（48）与地址解码器电路（56），通过插入隔离缓冲器（52）。此外，通过在读取传送周期结束时进行第一抽头地址的预先加载（72）而不等待串行时钟信号（SC）开始读取周期，来减少串行访问时间。

3. 发明授权

US5245578A DRAM with a two stage voltage pull-down sense amplifier 失效
标题翻译： DRAM具有两级电压下拉读出放大器
公开(公告)号：US5245578A
公开(公告)日：1993-09-14
申请号：US930138
申请日：1992-08-12
申请人： Loren L. McLaury
发明人： Loren L. McLaury
IPC分类号： G11C11/4091
CPC分类号： G11C11/4091
摘要： There is an integrated circuits that has an improved N-channel sense amplifier that increases the digital one and zero range. The invention spikes the lower voltage digit line closer to ground shortly before equilibrating with the higher voltage digit line.
摘要翻译：存在具有改进的N沟道读出放大器的集成电路，其增加数字的一个和零个范围。本发明在与较高电压数字线平衡之前不久即将较低电压数字线尖峰接近地面。

4. 发明授权

US07605602B1 Low-power output driver buffer circuit 有权
标题翻译：低功耗输出驱动缓冲电路
公开(公告)号：US07605602B1
公开(公告)日：2009-10-20
申请号：US12188120
申请日：2008-08-07
申请人： Nathan Robert Green , Loren L. McLaury
发明人： Nathan Robert Green , Loren L. McLaury
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00369 , H03K17/164
摘要： In one embodiment, an output driver buffer circuit for a logic device includes an output driver transistor adapted to adjust an output voltage of an output pad; a capacitor adapted to be connected to the transistor gate and further adapted when charged and connected to the gate to turn the transistor on; and a reference voltage source adapted to be connected to the transistor gate and further adapted when connected to the gate to maintain the transistor on. The reference voltage source is further adapted to be connected to the transistor gate after the capacitor has turned the transistor on and independent of the level of the output voltage of the output pad.
摘要翻译：在一个实施例中，用于逻辑器件的输出驱动器缓冲电路包括适于调整输出焊盘的输出电压的输出驱动晶体管; 电容器，适于连接到晶体管栅极，并进一步适于当充电并连接到栅极以使晶体管导通时; 以及参考电压源，其适于连接到所述晶体管栅极，并且当连接到所述栅极时进一步适配以维持所述晶体管导通。参考电压源还适于在电容器已经打开晶体管并且独立于输出焊盘的输出电压的电平之后连接到晶体管栅极。

5. 发明授权

US07512015B1 Negative voltage blocking for embedded memories 有权
标题翻译：嵌入式存储器的负电压阻塞
公开(公告)号：US07512015B1
公开(公告)日：2009-03-31
申请号：US11487751
申请日：2006-07-17
申请人： Loren L. McLaury
发明人： Loren L. McLaury
IPC分类号： G11C11/34
CPC分类号： G11C5/145 , G11C16/10 , G11C16/30
摘要： In one embodiment, a memory is provided that includes: a memory cell array adapted to be programmed with a positive voltage from a positive-negative node and to be erased with a negative voltage from the positive-negative node; a negative voltage blocking circuit; and a positive voltage source operable coupled to the negative voltage blocking circuit, the positive voltage source operable to provide the positive voltage to the positive-negative node through the negative voltage blocking circuit, wherein the negative voltage blocking circuit is adapted to prevent the negative voltage from coupling from the positive-negative node to the positive voltage source.
摘要翻译：在一个实施例中，提供了一种存储器，其包括：存储单元阵列，其适于用来自正负节点的正电压进行编程，并从正负节点用负电压擦除; 负压阻电路; 以及正电压源，其可操作地耦合到所述负电压阻断电路，所述正电压源可操作以通过所述负电压阻断电路向所述正负节点提供所述正电压，其中所述负电压阻断电路适于防止所述负电压从正负极耦合到正电压源。

6. 发明授权

US07411414B1 Single-ended output driver buffer 有权
标题翻译：单端输出驱动缓冲区
公开(公告)号：US07411414B1
公开(公告)日：2008-08-12
申请号：US11877434
申请日：2007-10-23
申请人： Nathan Robert Green , Loren L. McLaury
发明人： Nathan Robert Green , Loren L. McLaury
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00369 , H03K17/164
摘要： Circuits and related methods are provided for buffering reference voltages from noise associated with output driver transistors. In one example, an output driver buffer circuit includes an output driver transistor adapted to adjust an output voltage of an output pad. The circuit also includes a pre-driver circuit connected to a gate of the output driver transistor. The pre-driver circuit is adapted to receive a reference voltage to control the output driver transistor. The pre-driver circuit includes a precharged capacitor, a first switch adapted to connect the capacitor to the gate, and a second switch adapted to connect the reference voltage to the gate. The second switch is adapted to operate following a time period after the capacitor is connected to the gate. The capacitor is adapted to buffer noise associated with the output driver transistor during the time period.
摘要翻译：提供电路和相关方法用于从与输出驱动器晶体管相关联的噪声缓冲参考电压。在一个示例中，输出驱动器缓冲电路包括适于调节输出焊盘的输出电压的输出驱动器晶体管。该电路还包括连接到输出驱动晶体管的栅极的预驱动电路。预驱动电路适于接收参考电压以控制输出驱动晶体管。预驱动器电路包括预充电电容器，适于将电容器连接到栅极的第一开关和适于将参考电压连接到栅极的第二开关。第二开关适于在电容器连接到栅极之后的时间段之后进行操作。该电容器适于在该时间段期间缓冲与输出驱动晶体管相关联的噪声。

7. 发明授权

US06549481B2 Power up initialization circuit responding to an input signal 失效
公开(公告)号：US06549481B2
公开(公告)日：2003-04-15
申请号：US10078641
申请日：2002-02-19
申请人： Loren L. McLaury
发明人： Loren L. McLaury
IPC分类号： G11C700
CPC分类号： G11C11/4072 , G11C5/143 , G11C7/20 , G11C7/22 , G11C8/18
摘要： A power up pulse generator circuit generates a pulse of predetermined duration in spite of a slow rate of change of applied power supply voltage. The circuit has application to integrated logic circuits that begin operation from an initial condition after the application of the power supply voltage and an input signal. In one embodiment, a dynamic random access memory (DRAM) of the present invention begins operation after receiving an address strobe signal. The address strobe signal is coupled to the power up pulse generator circuit to assure that the power up pulse is of sufficient duration to reset internal registers and so establish the initial condition. The power up pulse generator circuit of such an embodiment includes a selectively enabled input buffer, a selectively enabled one shot, and a flip flop designed to assume a predetermined state on application of the power supply voltage.

8. 发明授权

US06424594B1 Method and apparatus for multiple latency synchronous dynamic random access memory 有权
公开(公告)号：US06424594B1
公开(公告)日：2002-07-23
申请号：US09930761
申请日：2001-08-14
申请人： Loren L. McLaury
发明人： Loren L. McLaury
IPC分类号： G11C800
CPC分类号： G11C7/1072 , G11C7/1039
摘要： A multiple latency synchronous dynamic random access memory includes separate two and three latency control circuits driven by an input latch circuit. Commands received at the multiple latency synchronous dynamic random access memory are converted to a separate set of command signals clocked through an input latch circuit by a feedback reset signal, such that commands are pipelined for three latency operation. In response to the command signals, the two latency control circuit produces a set of control signals according to a two latency algorithm. In response to the same command signals, the three latency control circuit independently produces a set of three latency control signals according to a three latency algorithm. In two latency operation, access time for signal development is externally controlled, while in three latency operation access time is internally controlled. In three latency operation, signal development time is determined separately for reads and writes. Also, in three latency operation, data is clocked along a data input path with a write latency. The multiple latency synchronous dynamic random access memory includes a pair of output data paths having different delays, where the data path is selected according to two or three latency operation.

9. 发明授权

US5901111A Enhanced multiple block writes to adjacent block of memory using a sequential counter 失效
标题翻译：使用顺序计数器增强对相邻内存块的多块写入
公开(公告)号：US5901111A
公开(公告)日：1999-05-04
申请号：US907396
申请日：1997-08-07
申请人： Loren L. McLaury , Donald M. Morgan
发明人： Loren L. McLaury , Donald M. Morgan
IPC分类号： G11C11/401 , G11C7/10 , G11C8/04 , G11C8/12 , G11C11/408 , G11C8/00
CPC分类号： G11C7/1021 , G11C7/1075 , G11C8/04 , G11C8/12
摘要： A memory device includes an array of randomly addressable registers. Blocks of the addressable registers are addressable by an address for block writing during a block write cycle. The blocks are of the size n, wherein n is the number of bits per plane of memory being written during the block write cycle. The device further includes a sequential counter for incrementing the address by n during burst mode when a block write is performed during a block write cycle to address a next addressable register of the array of randomly addressable registers.
摘要翻译：存储器件包括可随机寻址寄存器的阵列。可寻址寄存器的块可通过块写入周期期间的块写入的地址寻址。块的大小为n，其中n是在块写入周期期间被写入的每个存储器平面的位数。该装置还包括一个顺序计数器，用于当在块写入周期期间执行块写入以寻址随机寻址寄存器阵列的下一可寻址寄存器时，在突发模式期间将地址递增n。

10. 发明授权

US5754478A Fast, low power, write scheme for memory circuits using pulsed off isolation device 失效
公开(公告)号：US5754478A
公开(公告)日：1998-05-19
申请号：US515864
申请日：1995-08-16
申请人： Donald M. Morgan , Loren L. McLaury
发明人： Donald M. Morgan , Loren L. McLaury
IPC分类号： G11C7/06 , G11C7/18 , G11C11/4091 , G11C11/4097 , G11C7/00
CPC分类号： G11C11/4091 , G11C11/4097 , G11C7/06 , G11C7/18 , G11C2207/002 , G11C2207/005
摘要： A circuit, for controlling a write operation during which data from data lines is written to a memory cell, is used with a memory cell of the type that is connected to a row line and a first column line. An amplifier is connected across the first column line and a column line complimentary to the first column line. The column lines have a capacitance associated therewith. The circuit includes a control circuit for generating switching control signals. Switches are provided which are positioned in the column lines and are responsive to the switching control signals for selectively isolating at least a portion of the column lines during a predetermined portion of the write operation.

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