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1. 发明申请

US20100173496A1 PROFILE AND CD UNIFORMITY CONTROL BY PLASMA OXIDATION TREATMENT 有权
标题翻译：简介和CD等离子体氧化处理的均匀性控制
公开(公告)号：US20100173496A1
公开(公告)日：2010-07-08
申请号：US12350060
申请日：2009-01-07
申请人： Qinghua Zhong , Sung Cho , Gowri Kamarthy , Linda Braly
发明人： Qinghua Zhong , Sung Cho , Gowri Kamarthy , Linda Braly
IPC分类号： H01L21/4757
CPC分类号： H01L21/32105 , H01L21/02323 , H01L21/02326 , H01L21/31116 , H01L29/6656
摘要： A method of forming spacers from a non-silicon oxide, silicon containing spacer layer with horizontal surfaces and sidewall surfaces over a substrate is provided. A plasma oxidation treatment is provided to form a silicon oxide coating over the spacer layer, wherein the silicon oxide coating provides a horizontal coating on the horizontal surfaces and sidewall coatings on the sidewall surfaces of the spacer layer. An anisotropic main etch that selectively etches horizontal surfaces of the spacer layer and silicon oxide coating with respect to sidewall surfaces of the spacer layer and the sidewall coatings of the silicon oxide coating is provided. The spacer layer is etched, wherein the sidewall coatings of the silicon oxide coating protect sidewall surfaces of the spacer layer.
摘要翻译：提供了一种从非氧化硅形成间隔物的方法，在衬底上方具有水平表面和侧壁表面的含硅隔离层。提供等离子体氧化处理以在间隔层上形成氧化硅涂层，其中氧化硅涂层在间隔层的侧壁表面上的水平表面和侧壁涂层上提供水平涂层。提供了选择性地蚀刻间隔层和氧化硅涂层的水平表面相对于间隔层的侧壁表面和氧化硅涂层的侧壁涂层的各向异性主蚀刻。间隔层被蚀刻，其中氧化硅涂层的侧壁涂层保护间隔层的侧壁表面。

2. 发明授权

US07204934B1 Method for planarization etch with in-situ monitoring by interferometry prior to recess etch 有权
标题翻译：在凹陷蚀刻之前用干涉测量法进行原位监测的平面蚀刻方法
公开(公告)号：US07204934B1
公开(公告)日：2007-04-17
申请号：US10002676
申请日：2001-10-31
申请人： Linda Braly , Vahid Vahedi , Erik Edelberg , Alan Miller
发明人： Linda Braly , Vahid Vahedi , Erik Edelberg , Alan Miller
IPC分类号： H01L21/66 , G01L21/30
CPC分类号： H01L21/7684 , H01L21/32115 , H01L21/32137 , H01L21/763
摘要： A method for processing recess etch operations in substrates is provided including forming a hard mask over the substrate and etching a trench in the substrate using the hard mask, and forming a dielectric layer over the hard mask and in the trench, where the dielectric layer lines the trench. A conductive material is then applied over the dielectric layer such that a blanket of the conductive material lies over the hard mask and fills the trench, and the conductive material is etched to substantially planarize the conductive material. The etching of the conductive material triggers an endpoint just before all of the conductive material is removed from over the dielectric layer that overlies the bard mask. The conductive material is recess etched to remove the conductive material over the dielectric layer that overlies the hard mask and removes at least part of the conductive material from within the trench.
摘要翻译：提供了一种用于在衬底中处理凹陷蚀刻操作的方法，包括在衬底上形成硬掩模并使用硬掩模蚀刻衬底中的沟槽，以及在硬掩模和沟槽中形成电介质层，其中电介质层线沟渠。然后将导电材料施加在介电层上，使得导电材料的覆盖层位于硬掩模上方并填充沟槽，并且蚀刻导电材料以使导电材料基本上平坦化。导电材料的蚀刻恰好在所有的导电材料从覆盖在吟诵掩模上的电介质层上除去之前触发端点。导电材料被凹入蚀刻以去除覆盖在硬掩模上的电介质层上的导电材料，并从沟槽内去除至少一部分导电材料。

3. 发明授权

US08901004B2 Plasma etch method to reduce micro-loading 有权
标题翻译：等离子蚀刻法减少微载荷
公开(公告)号：US08901004B2
公开(公告)日：2014-12-02
申请号：US12840034
申请日：2010-07-20
申请人： Tom Kamp , Qian Fu , I. C. Jang , Linda Braly , Shenjian Liu
发明人： Tom Kamp , Qian Fu , I. C. Jang , Linda Braly , Shenjian Liu
IPC分类号： H01L21/311 , C03C15/00 , C03C25/68 , C23F1/00 , H01L21/768 , H01L21/3065
CPC分类号： H01L21/76816 , H01L21/3065
摘要： A method of producing plurality of etched features in an electronic device is disclosed that avoids micro-loading problems thus maintaining more uniform sidewall profiles and more uniform critical dimensions. The method comprises performing a first time-divisional plasma etch process step within a plasma chamber to a first depth of the plurality of etched features, and performing a flash process step to remove any polymers from exposed surfaces of the plurality of etched features without requiring an oxidation step. The flash process step is performed independently of the time-divisional plasma etch step. A second time-divisional plasma etch process step is performed within the plasma chamber to a second depth of the plurality of etched features. The method may be repeated until a desired etch depth is reached.
摘要翻译：公开了一种在电子设备中产生多个蚀刻特征的方法，其避免微加载问题，从而保持更均匀的侧壁轮廓和更均匀的临界尺寸。该方法包括在等离子体室内执行第一时分等离子体蚀刻工艺步骤至多个蚀刻特征的第一深度，以及执行闪光处理步骤以从多个蚀刻特征的暴露表面去除任何聚合物，而不需要氧化步骤。独立于分时等离子体蚀刻步骤执行闪光处理步骤。在等离子体室内执行第二分时等离子体蚀刻工艺步骤到多个蚀刻特征的第二深度。可以重复该方法直到达到期望的蚀刻深度。

4. 发明申请

US20110021029A1 PLASMA ETCH METHOD TO REDUCE MICRO-LOADING 有权
标题翻译：降低微载物的等离子体蚀刻方法
公开(公告)号：US20110021029A1
公开(公告)日：2011-01-27
申请号：US12840034
申请日：2010-07-20
申请人： Tom Kamp , Qian Fu , I.C. Jang , Linda Braly , Shenjian Liu
发明人： Tom Kamp , Qian Fu , I.C. Jang , Linda Braly , Shenjian Liu
IPC分类号： H01L21/465
CPC分类号： H01L21/76816 , H01L21/3065
摘要： A method of producing plurality of etched features in an electronic device is disclosed that avoids micro-loading problems thus maintaining more uniform sidewall profiles and more uniform critical dimensions. The method comprises performing a first time-divisional plasma etch process step within a plasma chamber to a first depth of the plurality of etched features, and performing a flash process step to remove any polymers from exposed surfaces of the plurality of etched features without requiring an oxidation step. The flash process step is performed independently of the time-divisional plasma etch step. A second time-divisional plasma etch process step is performed within the plasma chamber to a second depth of the plurality of etched features. The method may be repeated until a desired etch depth is reached.
摘要翻译：公开了一种在电子设备中产生多个蚀刻特征的方法，其避免微加载问题，从而保持更均匀的侧壁轮廓和更均匀的临界尺寸。该方法包括在等离子体室内执行第一时分等离子体蚀刻工艺步骤至多个蚀刻特征的第一深度，以及执行闪光处理步骤以从多个蚀刻特征的暴露表面去除任何聚合物，而不需要氧化步骤。独立于分时等离子体蚀刻步骤执行闪光处理步骤。在等离子体室内执行第二分时等离子体蚀刻工艺步骤到多个蚀刻特征的第二深度。可以重复该方法直到达到期望的蚀刻深度。

5. 发明授权

US08298949B2 Profile and CD uniformity control by plasma oxidation treatment 有权
标题翻译：通过等离子体氧化处理的轮廓和CD均匀性控制
公开(公告)号：US08298949B2
公开(公告)日：2012-10-30
申请号：US12350060
申请日：2009-01-07
申请人： Qinghua Zhong , Sung Cho , Gowri Kamarthy , Linda Braly
发明人： Qinghua Zhong , Sung Cho , Gowri Kamarthy , Linda Braly
IPC分类号： H01L21/311
CPC分类号： H01L21/32105 , H01L21/02323 , H01L21/02326 , H01L21/31116 , H01L29/6656
摘要： A method of forming spacers from a non-silicon oxide, silicon containing spacer layer with horizontal surfaces and sidewall surfaces over a substrate is provided. A plasma oxidation treatment is provided to form a silicon oxide coating over the spacer layer, wherein the silicon oxide coating provides a horizontal coating on the horizontal surfaces and sidewall coatings on the sidewall surfaces of the spacer layer. An anisotropic main etch that selectively etches horizontal surfaces of the spacer layer and silicon oxide coating with respect to sidewall surfaces of the spacer layer and the sidewall coatings of the silicon oxide coating is provided. The spacer layer is etched, wherein the sidewall coatings of the silicon oxide coating protect sidewall surfaces of the spacer layer.
摘要翻译：提供了一种从非氧化硅形成间隔物的方法，在衬底上方具有水平表面和侧壁表面的含硅隔离层。提供等离子体氧化处理以在间隔层上形成氧化硅涂层，其中氧化硅涂层在间隔层的侧壁表面上的水平表面和侧壁涂层上提供水平涂层。提供了选择性地蚀刻间隔层和氧化硅涂层的水平表面相对于间隔层的侧壁表面和氧化硅涂层的侧壁涂层的各向异性主蚀刻。间隔层被蚀刻，其中氧化硅涂层的侧壁涂层保护间隔层的侧壁表面。

6. 发明授权

US07303999B1 Multi-step method for etching strain gate recesses 有权
标题翻译：用于蚀刻应变栅极凹槽的多步法
公开(公告)号：US07303999B1
公开(公告)日：2007-12-04
申请号：US11395921
申请日：2006-03-31
申请人： Saravanapriyan Sriraman , Linda Braly
发明人： Saravanapriyan Sriraman , Linda Braly
IPC分类号： H01L21/302
CPC分类号： H01L21/32137 , H01L29/66636
摘要： Methods of performing controllable lateral etches into the silicon layer using a plasma-enhanced etch-deposit-etch sequence are disclosed. The first etch step etches into the silicon layer. The deposition step passivates horizontal surfaces, including the bottom of the etched feature. The second etch step increases the lateral undercut, resulting in a low V:L ratio silicon layer etch.
摘要翻译：公开了使用等离子体增强蚀刻沉积蚀刻顺序对硅层进行可控横向蚀刻的方法。第一蚀刻步骤蚀刻到硅层中。沉积步骤钝化水平表面，包括蚀刻特征的底部。第二蚀刻步骤增加了横向底切，导致低层V：L比硅层蚀刻。

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