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    • 4. 发明授权
    • Measurement based voltage stability monitoring and control
    • 基于测量的电压稳定性监测和控制
    • US08126667B2
    • 2012-02-28
    • US12131997
    • 2008-06-03
    • Pei ZhangLiang MinJian Chen
    • Pei ZhangLiang MinJian Chen
    • G01R25/00
    • G05F1/70H02J3/14
    • A measurement base voltage stability monitoring and control scheme having a means for measuring current and voltage phasors at a boundary bus of a load center; and an equivalent network having a fictitious bus with an aggregate load representative of all loads of the load center. The scheme further includes a computing device to calculate a voltage stability margin index based on the aggregate load of the fictitious bus and compare the voltage stability margin index to a pre-set threshold. The computing device causes an action to take place based on the comparison between the voltage stability margin index and the pre-set threshold.
    • 一种测量基础电压稳定性监视和控制方案,具有用于在负载中心的边界总线处测量电流和电压相量的装置; 以及具有代表负载中心的所有负载的总负载的虚拟总线的等效网络。 该方案还包括计算装置,用于基于虚拟总线的总负载来计算电压稳定裕度指数,并将电压稳定裕度指数与预设阈值进行比较。 计算装置根据电压稳定性裕度指数与预设阈值之间的比较,导致动作发生。
    • 7. 发明申请
    • METHOD AND APPARATUS FOR SHARED LINE UNIFIED CACHE
    • 用于共享线路统一高速缓存的方法和装置
    • US20150178199A1
    • 2015-06-25
    • US14137359
    • 2013-12-20
    • Liang-Min WangJohn M. MorganNamakkal N. Venkatesan
    • Liang-Min WangJohn M. MorganNamakkal N. Venkatesan
    • G06F12/08
    • G06F12/084G06F12/0811G06F12/082G06F12/0831G06F12/126G06F2212/1016G06F2212/6042Y02D10/13
    • An apparatus and method for implementing a shared unified cache. For example, one embodiment of a processor comprises: a plurality of processor cores grouped into modules, wherein each module has at least two processor cores grouped therein; a plurality of level 1 (L1) caches, each L1 cache directly accessible by one of the processor cores; a level 2 (L2) cache associated with each module, the L2 cache directly accessible by each of the processor cores associated with its respective module; a shared unified cache to store data and/or instructions for each of the processor cores in each of the modules; and a cache management module to manage the cache lines in the shared unified cache using a first cache line eviction policy favoring cache lines which are shared across two or more modules and which are accessed relatively more frequently from the modules.
    • 一种用于实现共享统一缓存的装置和方法。 例如,处理器的一个实施例包括:分组为模块的多个处理器核心,其中每个模块具有分组在其中的至少两个处理器核心; 多个级别1(L1)高速缓存,每个L1高速缓存可由所述处理器核心之一直接访问; 与每个模块相关联的级别2(L2)缓存,所述L2高速缓存可由与其相应模块相关联的每个处理器核心直接访问; 共享统一缓存,用于存储每个模块中每个处理器核心的数据和/或指令; 以及高速缓存管理模块,用于使用第一高速缓存行驱逐策略来管理共享统一高速缓存中的高速缓存行,所述第一高速缓存行驱逐策略有利于在两个或更多个模块之间共享的高速缓存行,并且被从模块相对更频繁地访问。