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1. 发明授权

US06566208B2 Method to form elevated source/drain using poly spacer 失效
公开(公告)号：US06566208B2
公开(公告)日：2003-05-20
申请号：US09912607
申请日：2001-07-25
申请人： Yang Pan , Lee Yong Meng , Leung Ying Keung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundarensan
发明人： Yang Pan , Lee Yong Meng , Leung Ying Keung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundarensan
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2257 , H01L29/41775 , H01L29/41783 , H01L29/665 , H01L29/6656
摘要： A method for forming a sub-quarter micron MOSFET having an elevated source/drain structure is described. A gate electrode is formed over a gate dielectric on a semiconductor substrate. Ions are implanted into the semiconductor substrate to form lightly doped regions using the gate electrode as a mask. Thereafter, dielectric spacers are formed on sidewalls of the gate electrode. A polysilicon layer is deposited overlying the semiconductor substrate, gate electrode, and dielectric spacers wherein the polysilicon layer is heavily doped. The polysilicon layer is etched back to leave polysilicon spacers on the dielectric spacers. Dopant is diffused from the polysilicon spacers into the semiconductor substrate to form source and drain regions underlying the polysilicon spacers. The polysilicon spacer on an end of the gate electrode is removed to separate the polysilicon spacers into a source polysilicon spacer and a drain polysilicon spacer thereby completing formation of a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device.

2. 发明授权

US06403485B1 Method to form a low parasitic capacitance pseudo-SOI CMOS device 有权
标题翻译：形成低寄生电容伪SOI CMOS器件的方法
公开(公告)号：US06403485B1
公开(公告)日：2002-06-11
申请号：US09846177
申请日：2001-05-02
申请人： Elgin Quek , Ravi Sundaresan , Yang Pan , James Lee Yong Meng , Ying Keung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan
发明人： Elgin Quek , Ravi Sundaresan , Yang Pan , James Lee Yong Meng , Ying Keung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan
IPC分类号： H01L21302
CPC分类号： H01L21/76895
摘要： A method of forming a pseudo-SOI device having elevated source/drain (S/D) regions that can be extended for use as local interconnect is described. Shallow trench isolation (STI) regions separating adjacent active regions are provided within a semiconductor substrate. Polysilicon gate electrodes and associated SID extensions are fabricated in and on the substrate in the active regions wherein a hard mask layer overlies each of the gate electrodes. Dielectric spacers are formed on sidewalls of each of the gate electrodes. A polysilicon layer is deposited overlying the gate electrodes and the substrate. The polysilicon layer is polished back with a polish stop at the hard mask layer. The polysilicon layer is etched back whereby the polysilicon layer is recessed with respect to the gate electrodes. Thereafter, the polysilicon layer is etched away overlying the STI regions where a separation between adjacent active areas is desired. If a local interconnect is desired between adjacent active areas, the polysilicon layer is not etched away overlying the STI region separating those active areas. The hard mask layer is removed. Ions are implanted and driven in to form elevated S/D regions within the polysilicon layer adjacent to the gate electrodes to complete formation of transistors having elevated S/D regions.
摘要翻译：描述了一种形成具有可扩展的用于局部互连的源/漏（S / D）区域较高的伪SOI器件的方法。分离相邻有源区的浅沟槽隔离（STI）区域设置在半导体衬底内。多晶硅栅极电极和相关的SID延伸部分在其中硬掩模层覆盖每个栅极电极的有源区域内和衬底上制造。在每个栅电极的侧壁上形成电介质间隔物。沉积覆盖栅电极和衬底的多晶硅层。在硬掩模层上用抛光光阑抛光多晶硅层。多晶硅层被回蚀，由此多晶硅层相对于栅电极凹陷。此后，将多晶硅层蚀刻掉，覆盖STI区域，其中期望相邻的有源区域之间的间隔。如果在相邻的有源区域之间需要局部互连，则多晶硅层不会被覆盖在分离这些有源区域的STI区域之上。去除硬掩模层。离子被植入和驱动以在与栅电极相邻的多晶硅层内形成升高的S / D区，以完成具有升高的S / D区的晶体管的形成。

3. 发明授权

US06544824B1 Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel 失效
标题翻译：通过首先形成栅/间隔堆叠形成垂直晶体管的方法，然后使用选择性外延形成源极，漏极和沟道
公开(公告)号：US06544824B1
公开(公告)日：2003-04-08
申请号：US10038390
申请日：2002-01-03
申请人： Yelehanka Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Lee Yong Meng , Ying Keung
发明人： Yelehanka Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Lee Yong Meng , Ying Keung
IPC分类号： H01L2100
CPC分类号： H01L29/66666
摘要： A method of manufacturing a vertical transistor. A doped region is formed in a substrate. We form sequentially on the substrate: a first spacer dielectric layer, a first gate electrode, a second spacer dielectric layer, a second gate electrode and a third spacer dielectric layer. A trench is formed through the first spacer dielectric layer, the first gate electrode, the second spacer dielectric layer, the second gate electrode and the third spacer dielectric layer. The trench has sidewalls. A gate dielectric layer is formed over the sidewalls of the trench. We form sequentially, in the trench: a first doped layer, a first channel layer, a second doped layer, a third doped layer, a second channel layer, and a fourth doped layer. A cap layer is formed over the structure. Contacts are preferably formed to the doped region, doped layers and gate electrodes.
摘要翻译：一种垂直晶体管的制造方法。在衬底中形成掺杂区域。我们在衬底上依次形成：第一间隔电介质层，第一栅电极，第二间隔电介质层，第二栅电极和第三间隔电介质层。通过第一间隔电介质层，第一栅电极，第二间隔电介质层，第二栅电极和第三间隔电介质层形成沟槽。沟槽有侧壁。栅极电介质层形成在沟槽的侧壁上。我们在沟槽中依次形成：第一掺杂层，第一沟道层，第二掺杂层，第三掺杂层，第二沟道层和第四掺杂层。在该结构上形成盖层。触点优选地形成于掺杂区域，掺杂层和栅电极。

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