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1. 发明授权

US07550315B2 Method for fabricating semiconductor package with multi-layer die contact and external contact 有权
标题翻译：用于制造具有多层模接触和外部接触的半导体封装的方法
公开(公告)号：US07550315B2
公开(公告)日：2009-06-23
申请号：US11781256
申请日：2007-07-22
申请人： Victor Tan Cher ′Khng , Lee Kian Chai
发明人： Victor Tan Cher ′Khng , Lee Kian Chai
IPC分类号： H01L21/44
CPC分类号： H01L25/0657 , H01L21/4853 , H01L23/3128 , H01L23/49816 , H01L23/5383 , H01L23/5386 , H01L24/10 , H01L24/13 , H01L24/48 , H01L24/73 , H01L24/81 , H01L2224/0401 , H01L2224/05124 , H01L2224/05599 , H01L2224/05611 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/06135 , H01L2224/06136 , H01L2224/13 , H01L2224/13082 , H01L2224/13147 , H01L2224/13155 , H01L2224/1357 , H01L2224/13611 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13664 , H01L2224/13669 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2224/81192 , H01L2224/81801 , H01L2224/85399 , H01L2225/0651 , H01L2225/06586 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2224/13099 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external contacts formed as multi layered metal bumps that include a base layer, a bump layer, and a non-oxidizing outer layer. The external contacts are smaller and more uniform than conventional solder balls, and can be fabricated using low temperature deposition processes, such that package warpage is decreased. Further, the external contacts can be shaped by etching to have generally planar tip portions that facilitate bonding to electrodes of a supporting substrate. Die contacts on the substrate can also be formed as multi layered metal bumps having generally planar tip portions, such that the die can be flip chip mounted to the substrate. A method for fabricating the package includes the step of depositing the different layers for the metal bumps using electroless and electrolytic deposition, and then etching the different layers to shape the metal bumps.
摘要翻译：半导体封装包括由基板材料形成的基板，与基板结合的半导体管芯，以及管芯上的密封剂。封装还包括形成为多层金属凸块的外部触头的阵列，其包括基底层，凸块层和非氧化外层。外部触点比常规焊球更小和更均匀，并且可以使用低温沉积工艺制造，使得封装翘曲减小。此外，外部触点可以通过蚀刻成形，以具有促进结合到支撑衬底的电极的大致平坦的尖端部分。基板上的模具接触也可以形成为具有大致平坦的尖端部分的多层金属凸块，使得模具可以倒装芯片安装到基板上。一种用于制造封装的方法包括使用化学镀和电解沉积沉积金属凸块的不同层，然后蚀刻不同层以使金属凸块成形的步骤。

2. 发明授权

US07161236B2 Bow control in an electronic package 有权
公开(公告)号：US07161236B2
公开(公告)日：2007-01-09
申请号：US10118580
申请日：2002-04-08
申请人： Lee Choon Kuan , Lee Kian Chai
发明人： Lee Choon Kuan , Lee Kian Chai
IPC分类号： H01L23/48
CPC分类号： H01L23/562 , H01L21/563 , H01L23/49894 , H01L2924/0002 , H01L2924/3511 , H05K3/303 , H05K3/3436 , H05K2201/10568 , H05K2201/10734 , H05K2201/10977 , H05K2201/2036 , Y02P70/613 , Y10S438/926 , Y10S438/928 , Y10T428/24 , Y10T428/24802 , Y10T428/24917 , H01L2924/00
摘要： A package including a package substrate, a die-substrate assembly including a substrate including a plurality of layers including a layer having a mesh to stiffen the substrate adapted to mount one or more dice, one or more dice mounted on the substrate and a molding compound to attach the substrate to the package substrate.

3. 发明授权

US06638792B2 Method for fabricating BOC semiconductor package 有权
标题翻译：制造BOC半导体封装的方法
公开(公告)号：US06638792B2
公开(公告)日：2003-10-28
申请号：US10047903
申请日：2002-01-17
申请人： Chong Chin Hui , Lee Choon Kian , Lee Kian Chai
发明人： Chong Chin Hui , Lee Choon Kian , Lee Kian Chai
IPC分类号： H01L2144
CPC分类号： H01L23/49827 , H01L23/3114 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L2224/05599 , H01L2224/45124 , H01L2224/48091 , H01L2224/85399 , H01L2924/00014 , H01L2924/01039 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A BOC (board-on-chip) semiconductor package includes a semiconductor die having die contacts, a substrate bonded circuit side down to the die, and an adhesive layer bonding the substrate to the die. The substrate includes a circuit side having a pattern of conductors and wire bonding sites, and a back side having an array of external contacts (e.g., BGA solder balls) in electrical communication with the conductors. The bonding sites on the conductors overhang the peripheral edges of the substrate such that access is provided for bonding wires to the bonding sites and to the die contacts. Because the substrate is bonded circuit side down to the die, a loop height of the wires, and an overall height (profile) of the package are reduced by a thickness of the substrate. In addition, a planarity of molded segments that encapsulate the wires is improved, and mold bleed during molding of the molded segments is reduced. A method for fabricating the BOC package includes the steps of: providing the die with the die contacts, providing the substrate with the conductors and the overhanging wire bonding sites on the circuit side and external contacts on the back side, bonding the substrate circuit side down to the die, wire bonding the wires to the wire bonding sites and to the die contacts, and then forming the molded segments to encapsulate the wires.
摘要翻译： BOC（片上电路板）半导体封装包括具有裸片接触的半导体管芯，向下延伸到管芯的衬底接合电路侧，以及将衬底粘合到管芯上的粘合剂层。衬底包括具有导体图案和引线接合位置的电路侧，以及具有与导体电连通的外部触头（例如，BGA焊球）的阵列的背面。导体上的结合位置突出于基板的周缘，使得提供接合以将接合线接合到接合位置和接头。由于基板的接合电路侧朝向芯片，电线的环路高度以及封装的整体高度（外形）被减小了基板的厚度。此外，改善了封装线的模制段的平面度，并且模制段的模制期间的模具流出减少。一种用于制造BOC封装的方法包括以下步骤：向芯片提供裸片触点，为基板提供导体和电路侧的突出引线接合位置以及背面的外部触点，将基板电路侧向下将导线引线接合到引线接合部位和芯片触点，然后形成模制段以封装线。

4. 发明授权

US07235872B2 Bow control in an electronic package 有权
标题翻译：弓控制在一个电子包装
公开(公告)号：US07235872B2
公开(公告)日：2007-06-26
申请号：US10931844
申请日：2004-08-31
申请人： Lee Choon Kuan , Lee Kian Chai
发明人： Lee Choon Kuan , Lee Kian Chai
IPC分类号： H01L23/48
CPC分类号： H01L23/562 , H01L21/563 , H01L23/49894 , H01L2924/0002 , H01L2924/3511 , H05K3/303 , H05K3/3436 , H05K2201/10568 , H05K2201/10734 , H05K2201/10977 , H05K2201/2036 , Y02P70/613 , Y10S438/926 , Y10S438/928 , Y10T428/24 , Y10T428/24802 , Y10T428/24917 , H01L2924/00
摘要： A package including a package substrate, a die-substrate assembly including a substrate including a plurality of layers including a layer having a mesh to stiffen the substrate adapted to mount one or more dice, one or more dice mounted on the substrate and a molding compound to attach the substrate to the package substrate.
摘要翻译：一种包括封装基板的封装，包括基板的模具基板组件，所述基板包括多个层，所述基板包括具有网状物的层，所述层具有适于安装一个或多个骰子的基板以加固所述基板，一个或多个骰子安装在所述基板上，以将衬底附接到封装衬底。

5. 发明授权

US07202556B2 Semiconductor package having substrate with multi-layer metal bumps 有权
标题翻译：具有多层金属凸块的衬底的半导体封装
公开(公告)号：US07202556B2
公开(公告)日：2007-04-10
申请号：US10023049
申请日：2001-12-20
申请人： Victor Tan Cher 'Khng , Lee Kian Chai
发明人： Victor Tan Cher 'Khng , Lee Kian Chai
IPC分类号： H01L23/34 , H01L23/48 , H01L23/52 , H01L29/40 , H01L23/28
CPC分类号： H01L25/0657 , H01L21/4853 , H01L23/3128 , H01L23/49816 , H01L23/5383 , H01L23/5386 , H01L24/10 , H01L24/13 , H01L24/48 , H01L24/73 , H01L24/81 , H01L2224/0401 , H01L2224/05124 , H01L2224/05599 , H01L2224/05611 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/06135 , H01L2224/06136 , H01L2224/13 , H01L2224/13082 , H01L2224/13147 , H01L2224/13155 , H01L2224/1357 , H01L2224/13611 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13664 , H01L2224/13669 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2224/81192 , H01L2224/81801 , H01L2224/85399 , H01L2225/0651 , H01L2225/06586 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2224/13099 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external contacts formed as multi layered metal bumps that include a base layer, a bump layer, and a non-oxidizing outer layer. The external contacts are smaller and more uniform than conventional solder balls, and can be fabricated using low temperature deposition processes, such that package warpage is decreased. Further, the external contacts can be shaped by etching to have generally planar tip portions that facilitate bonding to electrodes of a supporting substrate. Die contacts on the substrate can also be formed as multi layered metal bumps having generally planar tip portions, such that the die can be flip chip mounted to the substrate. A method for fabricating the package includes the step of depositing the different layers for the metal bumps using electroless and electrolytic deposition, and then etching the different layers to shape the metal bumps.
摘要翻译：半导体封装包括由基板材料形成的基板，与基板结合的半导体管芯，以及管芯上的密封剂。封装还包括形成为多层金属凸块的外部触头的阵列，其包括基底层，凸块层和非氧化外层。外部触点比常规焊球更小和更均匀，并且可以使用低温沉积工艺制造，使得封装翘曲减小。此外，外部触点可以通过蚀刻成形，以具有促进结合到支撑衬底的电极的大致平坦的尖端部分。基板上的模具接触也可以形成为具有大致平坦的尖端部分的多层金属凸块，使得模具可以倒装芯片安装到基板上。一种用于制造封装的方法包括使用化学镀和电解沉积沉积金属凸块的不同层，然后蚀刻不同层以使金属凸块成形的步骤。

6. 发明授权

US07465488B2 Bow control in an electronic package 有权
标题翻译：弓控制在一个电子包装
公开(公告)号：US07465488B2
公开(公告)日：2008-12-16
申请号：US11457223
申请日：2006-07-13
申请人： Lee Choon Kuan , Lee Kian Chai
发明人： Lee Choon Kuan , Lee Kian Chai
IPC分类号： B32B3/00 , H01L23/52 , H01L29/40
CPC分类号： H01L23/562 , H01L21/563 , H01L23/49894 , H01L2924/0002 , H01L2924/3511 , H05K3/303 , H05K3/3436 , H05K2201/10568 , H05K2201/10734 , H05K2201/10977 , H05K2201/2036 , Y02P70/613 , Y10S438/926 , Y10S438/928 , Y10T428/24 , Y10T428/24802 , Y10T428/24917 , H01L2924/00
摘要： A package including a package substrate, a die-substrate assembly including a substrate including a plurality of layers including a layer having a mesh to stiffen the substrate adapted to mount one or more dice, one or more dice mounted on the substrate and a molding compound to attach the substrate to the package substrate. Various embodiments include a method comprising providing a substrate including a layer having an outer surface, depositing a metal layer on the outer surface, and etching the metal layer to form an opening, the opening enclosing an area on the outer surface to mount one or more dice.
摘要翻译：一种包括封装基板的封装，包括基板的模具基板组件，所述基板包括多个层，所述基板包括具有网状物的层，所述层具有适于安装一个或多个骰子的基板以加固所述基板，一个或多个骰子安装在所述基板上，以将衬底附接到封装衬底。各种实施例包括提供包括具有外表面的层的衬底，在外表面上沉积金属层并蚀刻金属层以形成开口的方法，该开口包围外表面上的区域以安装一个或多个骰子。

7. 发明授权

US07253022B2 Method for fabricating semiconductor package with multi-layer metal bumps 有权
标题翻译：制造具有多层金属凸块的半导体封装的方法
公开(公告)号：US07253022B2
公开(公告)日：2007-08-07
申请号：US10867530
申请日：2004-06-14
申请人： Victor Tan Cher 'Khng , Lee Kian Chai
发明人： Victor Tan Cher 'Khng , Lee Kian Chai
IPC分类号： H01L21/50 , H01L21/44
CPC分类号： H01L25/0657 , H01L21/4853 , H01L23/3128 , H01L23/49816 , H01L23/5383 , H01L23/5386 , H01L24/10 , H01L24/13 , H01L24/48 , H01L24/73 , H01L24/81 , H01L2224/0401 , H01L2224/05124 , H01L2224/05599 , H01L2224/05611 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/06135 , H01L2224/06136 , H01L2224/13 , H01L2224/13082 , H01L2224/13147 , H01L2224/13155 , H01L2224/1357 , H01L2224/13611 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13664 , H01L2224/13669 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2224/81192 , H01L2224/81801 , H01L2224/85399 , H01L2225/0651 , H01L2225/06586 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2224/13099 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external contacts formed as multi layered metal bumps that include a base layer, a bump layer, and a non-oxidizing outer layer. The external contacts are smaller and more uniform than conventional solder balls, and can be fabricated using low temperature deposition processes, such that package warpage is decreased. Further, the external contacts can be shaped by etching to have generally planar tip portions that facilitate bonding to electrodes of a supporting substrate. Die contacts on the substrate can also be formed as multi layered metal bumps having generally planar tip portions, such that the die can be flip chip mounted to the substrate. A method for fabricating the package includes the step of depositing the different layers for the metal bumps using electroless and electrolytic deposition, and then etching the different layers to shape the metal bumps.
摘要翻译：半导体封装包括由基板材料形成的基板，与基板结合的半导体管芯，以及管芯上的密封剂。封装还包括形成为多层金属凸块的外部触头的阵列，其包括基底层，凸块层和非氧化外层。外部触点比常规焊球更小和更均匀，并且可以使用低温沉积工艺制造，使得封装翘曲减小。此外，外部触点可以通过蚀刻成形，以具有促进结合到支撑衬底的电极的大致平坦的尖端部分。基板上的模具接触也可以形成为具有大致平坦的尖端部分的多层金属凸块，使得模具可以倒装芯片安装到基板上。一种用于制造封装的方法包括使用化学镀和电解沉积沉积金属凸块的不同层，然后蚀刻不同层以使金属凸块成形的步骤。

8. 发明授权

US06507114B2 BOC semiconductor package including a semiconductor die and a substrate bonded circuit side down to the die 有权
公开(公告)号：US06507114B2
公开(公告)日：2003-01-14
申请号：US09774130
申请日：2001-01-30
申请人： Chong Chin Hui , Lee Choon Kuan , Lee Kian Chai
发明人： Chong Chin Hui , Lee Choon Kuan , Lee Kian Chai
IPC分类号： H01L2348
CPC分类号： H01L23/49827 , H01L23/3114 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L2224/05599 , H01L2224/45124 , H01L2224/48091 , H01L2224/85399 , H01L2924/00014 , H01L2924/01039 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A BOC (board-on-chip) semiconductor package includes a semiconductor die having die contacts, a substrate bonded circuit side down to the die, and an adhesive layer bonding the substrate to the die. The substrate includes a circuit side having a pattern of conductors and wire bonding sites, and a back side having an array of external contacts (e.g., BGA solder balls) in electrical communication with the conductors. The bonding sites on the conductors overhang the peripheral edges of the substrate such that access is provided for bonding wires to the bonding sites and to the die contacts. Because the substrate is bonded circuit side down to the die, a loop height of the wires, and an overall height (profile) of the package are reduced by a thickness of the substrate. In addition, a planarity of molded segments that encapsulate the wires is improved, and mold bleed during molding of the molded segments is reduced. A method for fabricating the BOC package includes the steps of: providing the die with the die contacts, providing the substrate with the conductors and the overhanging wire bonding sites on the circuit side and external contacts on the back side, bonding the substrate circuit side down to the die, wire bonding the wires to the wire bonding sites and to the die contacts, and then forming the molded segments to encapsulate the wires.

9. 发明授权

US07208828B2 Semiconductor package with wire bonded stacked dice and multi-layer metal bumps 有权
标题翻译：半导体封装带导线接合的堆叠骰子和多层金属凸块
公开(公告)号：US07208828B2
公开(公告)日：2007-04-24
申请号：US11101626
申请日：2005-04-08
申请人： Victor Tan Cher 'Khng , Lee Kian Chai
发明人： Victor Tan Cher 'Khng , Lee Kian Chai
IPC分类号： H01L23/34 , H01L23/48 , H01L23/52 , H01L29/40 , H01L23/28
CPC分类号： H01L25/0657 , H01L21/4853 , H01L23/3128 , H01L23/49816 , H01L23/5383 , H01L23/5386 , H01L24/10 , H01L24/13 , H01L24/48 , H01L24/73 , H01L24/81 , H01L2224/0401 , H01L2224/05124 , H01L2224/05599 , H01L2224/05611 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/06135 , H01L2224/06136 , H01L2224/13 , H01L2224/13082 , H01L2224/13147 , H01L2224/13155 , H01L2224/1357 , H01L2224/13611 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13664 , H01L2224/13669 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2224/81192 , H01L2224/81801 , H01L2224/85399 , H01L2225/0651 , H01L2225/06586 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2224/13099 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external contacts formed as multi layered metal bumps that include a base layer, a bump layer, and a non-oxidizing outer layer. The external contacts are smaller and more uniform than conventional solder balls, and can be fabricated using low temperature deposition processes, such that package warpage is decreased. Further, the external contacts can be shaped by etching to have generally planar tip portions that facilitate bonding to electrodes of a supporting substrate. Die contacts on the substrate can also be formed as multi layered metal bumps having generally planar tip portions, such that the die can be flip chip mounted to the substrate. A method for fabricating the package includes the step of depositing the different layers for the metal bumps using electroless and electrolytic deposition, and then etching the different layers to shape the metal bumps.
摘要翻译：半导体封装包括由基板材料形成的基板，与基板结合的半导体管芯，以及管芯上的密封剂。封装还包括形成为多层金属凸块的外部触头的阵列，其包括基底层，凸块层和非氧化外层。外部触点比常规焊球更小和更均匀，并且可以使用低温沉积工艺制造，使得封装翘曲减小。此外，外部触点可以通过蚀刻成形，以具有促进结合到支撑衬底的电极的大致平坦的尖端部分。基板上的模具接触也可以形成为具有大致平坦的尖端部分的多层金属凸块，使得模具可以倒装芯片安装到基板上。一种用于制造封装的方法包括使用化学镀和电解沉积沉积金属凸块的不同层，然后蚀刻不同层以使金属凸块成形的步骤。

10. 发明授权

US06781248B2 Method for encapsulating intermediate conductive elements connecting a semiconductor die to a substrate and semiconductor devices so packaged 有权
标题翻译：用于封装将半导体管芯连接到衬底的中间导电元件和如此封装的半导体器件的方法
公开(公告)号：US06781248B2
公开(公告)日：2004-08-24
申请号：US09916197
申请日：2001-07-27
申请人： Chong Chin Hui , Lee Kian Chai , Jason Pittam
发明人： Chong Chin Hui , Lee Kian Chai , Jason Pittam
IPC分类号： H01L2156
CPC分类号： H01L23/3128 , H01L21/56 , H01L23/13 , H01L23/4985 , H01L24/48 , H01L24/97 , H01L2224/05599 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/85399 , H01L2924/00014 , H01L2924/01079 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/181 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A method for packaging semiconductor device assemblies. An assembly is formed which includes a semiconductor die, a tape positioned over the active surface of the die, and a substrate element positioned on an opposite side of the tape from the die. Bond pads of the die are exposed through a slot formed through the tape and an aligned opening formed through the substrate element facilitate the extension of intermediate conductive elements from the bond pads and through the slot and opening, to corresponding contact areas on the substrate element. One or both ends of the slot extend beyond an outer periphery of the die to facilitate introduction of an encapsulant material into a channel or receptacles defined by the slot, opening, and active surface of the semiconductor die. Prior to encapsulation, the side of the opening of the substrate element is sealed opposite the tape with a coverlay to contain the encapsulant material within the channel or receptacle. Assemblies and packages formed by the method are also disclosed.
摘要翻译：一种用于封装半导体器件组件的方法。形成了一个组件，其包括半导体管芯，位于管芯的有效表面上的带以及位于与管芯相反的带的另一侧上的衬底元件。管芯的接合焊盘通过穿过带形成的槽暴露，并且通过衬底元件形成的对准的开口促进中间导电元件从接合焊盘的延伸，并且通过槽和开口延伸到衬底元件上的对应的接触区域。槽的一端或两端延伸超过管芯的外周，以便于将密封剂材料引入由半导体管芯的槽，开口和有源表面限定的通道或插座中。在封装之前，衬底元件的开口侧面用带有覆盖层的带密封，以将密封剂材料容纳在通道或容器内。还公开了通过该方法形成的组件和封装。

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