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1. 发明授权

US06867078B1 Method for forming a microwave field effect transistor with high operating voltage 有权
标题翻译：用于形成具有高工作电压的微波场效应晶体管的方法
公开(公告)号：US06867078B1
公开(公告)日：2005-03-15
申请号：US10716955
申请日：2003-11-19
申请人： Bruce M. Green , Olin L. Hartin , Lawrence S. Klingbeil , Ellen Y. Lan , Hsin-Hua P. Li , Charles E. Weitzel
发明人： Bruce M. Green , Olin L. Hartin , Lawrence S. Klingbeil , Ellen Y. Lan , Hsin-Hua P. Li , Charles E. Weitzel
IPC分类号： H01L21/335 , H01L29/423 , H01L29/778 , H01L21/338 , H01L21/3205
CPC分类号： H01L29/66462 , H01L29/42316 , H01L29/7785
摘要： A microwave field effect transistor (10) has a high conductivity gate (44) overlying a double heterojunction structure (14, 18, 22) that has an undoped channel layer (18). The heterojunction structure overlies a substrate (12). A recess layer that is a not intentionally doped (NID) layer (24) overlies the heterojunction structure and is formed with a predetermined thickness that minimizes impact ionization effects at an interface of a drain contact of source/drain ohmic contacts (30) and permits significantly higher voltage operation than previous step gate transistors. Another recess layer (26) is used to define a gate dimension. A Schottky gate opening (42) is formed within a step gate opening (40) to create a step gate structure. A channel layer (18) material of InxGa1−xAs is used to provide a region of electron confinement with improved transport characteristics that result in higher frequency of operation, higher power density and improved power-added efficiency.
摘要翻译：微波场效应晶体管（10）具有覆盖具有未掺杂沟道层（18）的双异质结结构（14,18,22）的高导电性栅极（44）。异质结结构覆盖在基板（12）上。作为非有意掺杂（NID）层（24）的凹陷层覆盖在异质结结构上并形成预定的厚度，使得在源极/漏极欧姆接触（30）的漏极接触的界面处的冲击电离效应最小化并允许比上一级栅晶体管显着更高的电压操作。另一个凹陷层（26）用于限定门尺寸。肖特基门开口（42）形成在步进门开口（40）内以形成阶梯门结构。使用In x Ga 1-x As的沟道层（18）材料来提供具有改善的传输特性的电子约束区域，这导致更高的操作频率，更高的功率密度和更好的功率附加效率。

2. 发明授权

US5830774A Method for forming a metal pattern on a substrate 失效
标题翻译：在基板上形成金属图案的方法
公开(公告)号：US5830774A
公开(公告)日：1998-11-03
申请号：US667013
申请日：1996-06-24
申请人： Lawrence S. Klingbeil, Jr. , Marino J. Martinez , Ernest Schirmann , Gordon M. Grivna
发明人： Lawrence S. Klingbeil, Jr. , Marino J. Martinez , Ernest Schirmann , Gordon M. Grivna
IPC分类号： H01L21/28 , H01L21/033 , H01L21/3205 , H01L21/44 , H01L21/441
CPC分类号： H01L21/0331
摘要： A method for forming a metal pattern on a substrate (11) includes forming a dielectric stack (14) on a major surface (12) of the substrate (11) and forming a mask (22) on the dielectric stack (14). The dielectric stack (14) includes an aluminum nitride layer (16) serving as an etch stop layer between two dielectric layers (15, 17). An opening is formed in the dielectric stack (14) via successive etching. The etching of the dielectric layer (15) between the aluminum nitride layer (16) and the substrate (11) undercuts the aluminum nitride layer (16). A metal layer (30) is deposited on the major surface through the opening via sputtering. The metal layer (30) on the major surface is distinctively separated from a metal layer (34) on the edge of the opening. The mask (22) is dissolved in a solvent, thereby lifting-off a metal layer (34) deposited on the mask (22).
摘要翻译：在基板（11）上形成金属图案的方法包括在基板（11）的主表面（12）上形成介质叠层（14），并在介质叠层（14）上形成掩模（22）。电介质堆叠（14）包括用作两个电介质层（15,17）之间的蚀刻停止层的氮化铝层（16）。通过连续蚀刻在电介质堆叠（14）中形成开口。在氮化铝层（16）和衬底（11）之间的介电层（15）的蚀刻使氮化铝层（16）下切。通过溅射通过开口沉积在主表面上的金属层（30）。主表面上的金属层（30）与开口边缘上的金属层（34）有明显的分离。将掩模（22）溶解在溶剂中，从而剥离沉积在掩模（22）上的金属层（34）。

3. 发明授权

US08742599B2 Identification mechanism for semiconductor device die 有权
标题翻译：半导体器件芯片识别机制
公开(公告)号：US08742599B2
公开(公告)日：2014-06-03
申请号：US13599388
申请日：2012-08-30
申请人： Colby G. Rampley , Lawrence S. Klingbeil
发明人： Colby G. Rampley , Lawrence S. Klingbeil
IPC分类号： H01L23/49
CPC分类号： H01L23/48 , H01L23/544 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/85 , H01L2223/5442 , H01L2223/54433 , H01L2223/5448 , H01L2223/54486 , H01L2224/02379 , H01L2224/0345 , H01L2224/036 , H01L2224/05552 , H01L2224/05624 , H01L2224/05644 , H01L2224/06135 , H01L2224/06138 , H01L2924/00014 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method and system for uniquely identifying each semiconductor device die from a wafer is provided. Identifying features are associated with device die bond pads. In one embodiment, one or more tab features are patterned and associated with each of one or more device die bond pads. These features can represent a code (e.g., binary or ternary) that uniquely identifies each device die on the wafer. Each tab feature can be the same shape or different shapes, depending upon the nature of coding desired. Alternatively, portions of the one or more device die bond pads can be omitted as a mechanism for providing coded information, rather than adding portions to the device die bond pads.
摘要翻译：提供了用于从晶片唯一地识别每个半导体器件裸片的方法和系统。识别特征与器件管芯接合焊盘相关联。在一个实施例中，将一个或多个突片特征图案化并与一个或多个器件管芯接合焊盘中的每一个相关联。这些特征可以表示唯一地识别晶片上的每个器件裸片的代码（例如，二进制或三进制）。每个标签特征可以是相同的形状或不同的形状，这取决于所需编码的性质。或者，可以省略一个或多个器件管芯接合焊盘的部分作为用于提供编码信息的机构，而不是将部分添加到器件管芯接合焊盘。

4. 发明授权

US5882961A Method of manufacturing semiconductor device with reduced charge trapping 失效
标题翻译：制造具有减少的电荷捕获的半导体器件的方法
公开(公告)号：US5882961A
公开(公告)日：1999-03-16
申请号：US940097
申请日：1997-09-29
申请人： Lawrence S. Klingbeil, Jr. , Mark R. Wilson
发明人： Lawrence S. Klingbeil, Jr. , Mark R. Wilson
IPC分类号： H01L21/265 , H01L21/336 , H01L29/49 , H01L21/338
CPC分类号： H01L29/66575 , H01L21/26506 , H01L21/26586 , H01L29/4983 , H01L29/6656
摘要： A semiconductor device (20) is fabricated by doping a dielectric layer (29) located over the surface of a semiconductor substrate (21). The dielectric layer (29) contains nitrogen and is doped with silicon ions by using an ion implantation process (15) such that a peak concentration (32) of the silicon ions remains in the dielectric layer (29) during the ion implantation process (15). Doping the dielectric layer (29) reduces charge trapping in the dielectric layer (29) and reduces power slump in the semiconductor device (20) during high frequency operation.
摘要翻译：半导体器件（20）通过掺杂位于半导体衬底（21）的表面上的电介质层（29）来制造。电介质层（29）含有氮，并且通过使用离子注入工艺（15）掺杂硅离子，使得在离子注入过程（15）期间硅离子的峰值浓度（32）保留在电介质层（29）中）。在高频操作期间，掺杂介电层（29）可减少电介质层（29）中的电荷捕获并减少半导体器件（20）中的功率衰减。

5. 发明授权

US5688703A Method of manufacturing a gate structure for a metal semiconductor field effect transistor 失效
标题翻译：制造金属半导体场效应晶体管的栅极结构的方法
公开(公告)号：US5688703A
公开(公告)日：1997-11-18
申请号：US523710
申请日：1995-09-05
申请人： Lawrence S. Klingbeil, Jr. , Marino J. Martinez
发明人： Lawrence S. Klingbeil, Jr. , Marino J. Martinez
IPC分类号： H01L21/285 , H01L21/335 , H01L21/338 , H01L29/08 , H01L29/423
CPC分类号： H01L29/66878 , H01L21/28581 , H01L21/28587 , H01L29/0891 , H01L29/42316 , H01L29/66462 , Y10S148/105 , Y10S148/14
摘要： A method of manufacturing a gate structure (19) for a semiconductor device (10) utilizes a dielectric layer (17) containing aluminum to protect the surface of a substrate (11) from residues resulting from deposition and etching of the gate structure (19). The gate structure (19) forms a refractory contact to the substrate (11), and the source and drain regions (26) are self-aligned to the gate structure (19). Semiconductor devices manufactured using methods in accordance with the present invention are observed to have a higher breakdown voltage and a higher transconductance, among other improved electrical performance characteristics.
摘要翻译：制造半导体器件（10）的栅极结构（19）的方法利用包含铝的电介质层（17）来保护基板（11）的表面免受由栅极结构（19）的沉积和蚀刻所导致的残留物的影响，。栅极结构（19）与衬底（11）形成难熔接触，并且源极和漏极区域（26）与栅极结构（19）自对准。观察到使用根据本发明的方法制造的半导体器件具有更高的击穿电压和更高的跨导以及其它改进的电气性能特性。

6. 发明授权

US5631175A Method for fabricating an elevated-gate field effect transistor 失效
标题翻译：制造高栅极场效应晶体管的方法
公开(公告)号：US5631175A
公开(公告)日：1997-05-20
申请号：US587434
申请日：1996-01-17
申请人： James G. Gilbert , Lawrence S. Klingbeil, Jr. , David J. Halchin , John M. Golio
发明人： James G. Gilbert , Lawrence S. Klingbeil, Jr. , David J. Halchin , John M. Golio
IPC分类号： H01L21/338 , H01L29/08 , H01L29/10 , H01L29/812 , H01L21/8252
CPC分类号： H01L29/66878 , H01L29/0891 , H01L29/1029 , H01L29/812
摘要： A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative to the top surface (34, 36) of the active region (13) on either side of the gate (20). A fabrication method for the transistor (10) forms the elevated platform (18) by etching the active region surface (44) on both sides of the gate (20) so that the bottom surface (21) of the gate (20) is elevated relative to the top surface (34) of the surrounding active region (13). The gate (20) itself and/or a patterned photoresist layer (116) may be used as a mask for performing this etch.
摘要翻译：场效应晶体管（10）具有形成在衬底（12）中的有源层（16）。门（20）设置在由有源层（16）形成的升高的平台（18）上。升高的平台（18）相对于闸门（20）的任一侧上的有源区域（13）的顶表面（34,36）升高浇口（20）的底表面（21）。晶体管（10）的制造方法通过蚀刻栅极（20）两侧的有源区表面（44）形成升高的平台（18），使得栅极（20）的底表面（21）升高相对于周围活动区域（13）的顶表面（34）。栅极（20）本身和/或图案化的光致抗蚀剂层（116）可用作进行该蚀刻的掩模。

7. 发明授权

US09324667B2 Semiconductor devices with compliant interconnects 有权
标题翻译：具有兼容互连的半导体器件
公开(公告)号：US09324667B2
公开(公告)日：2016-04-26
申请号：US13350098
申请日：2012-01-13
申请人： Trent S. Uehling , Lawrence S. Klingbeil , Mostafa Vadipour , Brett P. Wilkerson , Leo M. Higgins, III
发明人： Trent S. Uehling , Lawrence S. Klingbeil , Mostafa Vadipour , Brett P. Wilkerson , Leo M. Higgins, III
IPC分类号： H01L21/4763 , H01L23/00
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/0345 , H01L2224/03462 , H01L2224/0347 , H01L2224/036 , H01L2224/0361 , H01L2224/03914 , H01L2224/0401 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/1146 , H01L2224/11472 , H01L2224/11849 , H01L2224/11906 , H01L2224/13017 , H01L2224/13018 , H01L2224/13022 , H01L2224/13023 , H01L2224/13082 , H01L2224/13083 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13564 , H01L2224/1357 , H01L2224/13611 , H01L2224/16237 , H01L2224/73204 , H01L2224/81191 , H01L2224/81193 , H01L2924/00014 , H01L2924/10253 , H01L2924/00 , H01L2924/00012 , H01L2924/01047 , H01L2224/05552
摘要： A method forms a connecting pillar to a bonding pad of an integrated circuit. A seed layer is formed over the bond pad. Photoresist is deposited over the integrated circuit. An opening is formed in the photoresist over the bond pad. The connecting pillar is formed in the opening by plating.
摘要翻译：一种方法形成到集成电路的焊盘的连接柱。在接合焊盘上形成种子层。光刻胶沉积在集成电路上。在接合焊盘上的光致抗蚀剂中形成开口。连接柱通过电镀形成在开口中。

8. 发明授权

US5508539A Elevated-gate field effect transistor structure and fabrication method 失效
标题翻译：高栅极场效应晶体管结构及制造方法
公开(公告)号：US5508539A
公开(公告)日：1996-04-16
申请号：US425733
申请日：1995-04-20
申请人： James G. Gilbert , Lawrence S. Klingbeil, Jr. , David J. Halchin , John M. Golio
发明人： James G. Gilbert , Lawrence S. Klingbeil, Jr. , David J. Halchin , John M. Golio
IPC分类号： H01L21/338 , H01L29/08 , H01L29/10 , H01L29/812 , H01L29/80 , H01L27/02
CPC分类号： H01L29/66878 , H01L29/0891 , H01L29/1029 , H01L29/812
摘要： A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative to the top surface (34, 36) of the active region (13) on either side of the gate (20). A fabrication method for the transistor (10) forms the elevated platform (18) by etching the active region surface (44) on both sides of the gate (20) so that the bottom surface (21) of the gate (20) is elevated relative to the top surface (34) of the surrounding active region (13). The gate (20) itself and/or a patterned photoresist layer (116) may be used as a mask for performing this etch.
摘要翻译：场效应晶体管（10）具有形成在衬底（12）中的有源层（16）。门（20）设置在由有源层（16）形成的升高的平台（18）上。升高的平台（18）相对于闸门（20）的任一侧上的有源区域（13）的顶表面（34,36）升高浇口（20）的底表面（21）。晶体管（10）的制造方法通过蚀刻栅极（20）两侧的有源区表面（44）形成升高的平台（18），使得栅极（20）的底表面（21）升高相对于周围活动区域（13）的顶表面（34）。栅极（20）本身和/或图案化的光致抗蚀剂层（116）可用作进行该蚀刻的掩模。

9. 发明授权

US5384273A Method of making a semiconductor device having a short gate length 失效
标题翻译：制造栅极长度短的半导体器件的方法
公开(公告)号：US5384273A
公开(公告)日：1995-01-24
申请号：US233290
申请日：1994-04-26
申请人： Robert B. Davies , Charles B. Anderson , Lawrence S. Klingbeil, Jr. , George B. Norris
发明人： Robert B. Davies , Charles B. Anderson , Lawrence S. Klingbeil, Jr. , George B. Norris
IPC分类号： H01L21/266 , H01L21/338 , H01L29/08 , H01L29/423 , H01L29/812 , H01L21/335 , H01L21/31
CPC分类号： H01L29/66878 , H01L21/266 , H01L29/0891 , H01L29/42316 , H01L29/812 , Y10S438/965
摘要： A semiconductor device having a short gate length is fabricated. The short gate length is obtained by utilizing the fact that an unannealed silicon nitride can be isotropically etched while not etching an annealed silicon nitride layer. The method comprises forming a first silicon nitride 13 on a semiconductor material 10, annealing layer 13, forming an insulating layer 15, a second silicon nitride layer 17 and a masking layer 19, undercutting a portion of layers 17 and 15, removing the masking layer, annealing the second silicon nitride 17, implanting to form channel region 20 having portions 21 and 22, undercutting a portion of the insulating layer 15, removing the second silicon nitride 17 and the first silicon nitride 13 not covered by layer 15, forming gate 23 having effective gate length 30 and source/drain 25/26.
摘要翻译：制造具有短栅极长度的半导体器件。通过利用非退火氮化硅可以在不蚀刻退火的氮化硅层的同时对其进行各向同性蚀刻的事实获得短栅极长度。该方法包括在半导体材料10上形成第一氮化硅13，退火层13，形成绝缘层15，第二氮化硅层17和掩模层19，对部分层17和15进行底切，去除掩模层退火第二氮化硅17，注入以形成具有部分21和22的沟道区20，对绝缘层15的一部分进行底切，去除未被层15覆盖的第二氮化硅17和第一氮化硅13，形成栅极23 具有有效的栅极长度30和源极/漏极25/26。

10. 发明申请

US20130181340A1 SEMICONDUCTOR DEVICES WITH COMPLIANT INTERCONNECTS 有权
标题翻译：具有兼容互连的半导体器件
公开(公告)号：US20130181340A1
公开(公告)日：2013-07-18
申请号：US13350098
申请日：2012-01-13
申请人： Trent S. UEHLING , Lawrence S. KLINGBEIL , Mostafa VADIPOUR , Brett P. WILKERSON , Leo M. HIGGINS, III
发明人： Trent S. UEHLING , Lawrence S. KLINGBEIL , Mostafa VADIPOUR , Brett P. WILKERSON , Leo M. HIGGINS, III
IPC分类号： H01L21/283 , H01L23/485
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/0345 , H01L2224/03462 , H01L2224/0347 , H01L2224/036 , H01L2224/0361 , H01L2224/03914 , H01L2224/0401 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/1146 , H01L2224/11472 , H01L2224/11849 , H01L2224/11906 , H01L2224/13017 , H01L2224/13018 , H01L2224/13022 , H01L2224/13023 , H01L2224/13082 , H01L2224/13083 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13564 , H01L2224/1357 , H01L2224/13611 , H01L2224/16237 , H01L2224/73204 , H01L2224/81191 , H01L2224/81193 , H01L2924/00014 , H01L2924/10253 , H01L2924/00 , H01L2924/00012 , H01L2924/01047 , H01L2224/05552
摘要： A method forms a connecting pillar to a bonding pad of an integrated circuit. A seed layer is formed over the bond pad. Photoresist is deposited over the integrated circuit. An opening is formed in the photoresist over the bond pad. The connecting pillar is formed in the opening by plating.
摘要翻译：一种方法形成到集成电路的焊盘的连接柱。在接合焊盘上形成种子层。光刻胶沉积在集成电路上。在接合焊盘上的光致抗蚀剂中形成开口。连接柱通过电镀形成在开口中。

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