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1. 发明授权

US6134130A Power reception circuits for a device receiving an AC power signal 失效
标题翻译：用于接收AC电力信号的设备的电力接收电路
公开(公告)号：US6134130A
公开(公告)日：2000-10-17
申请号：US356427
申请日：1999-07-19
申请人： Lawrence Edwin Connell , Patrick Lee Rakers , Timothy James Collins , Donald Bernard Lemersal, Jr.
发明人： Lawrence Edwin Connell , Patrick Lee Rakers , Timothy James Collins , Donald Bernard Lemersal, Jr.
IPC分类号： G06K19/07 , H02J5/00 , H02M7/217 , H02M5/42 , H02M7/00
CPC分类号： G06K19/0701 , G06K19/0723 , H02J5/005 , H02M7/217 , H04B5/0062 , H02M2001/4283 , Y02B70/126
摘要： Power reception circuits employable in portable data devices (e.g., smart cards) to derive power and/or data from an input AC power signal (e.g., an ASK modulated carrier signal). In one embodiment, the power reception circuit comprises a power rectifier (120), a shunt rectifier (142) and a shunting element (132). The power rectifier (120) is adapted to rectify the input power signal, yielding a rectified output waveform. The shunt rectifier (142) is connected in parallel with the power rectifier (120). The shunting element (132) is connected to the shunt rectifier (142) and is operable to regulate an output voltage or current waveform produced at the output of the power rectifier (120). In another embodiment, the power reception circuit includes an analog circuit (610) for recovering data from a modulated carrier signal. A decoupling device (630) isolates the analog circuit (610) from impedance variations of a load. A shunt device (640) diverts undesired current from the load.
摘要翻译：功率接收电路可用于便携式数据设备（例如，智能卡）中以从输入AC功率信号（例如，ASK调制载波信号）导出功率和/或数据。在一个实施例中，功率接收电路包括功率整流器（120），并联整流器（142）和分流元件（132）。功率整流器（120）适于对输入功率信号进行整流，产生经整流的输出波形。并联整流器（142）与电力整流器（120）并联连接。分流元件（132）连接到并联整流器（142）并且可操作以调节在功率整流器（120）的输出处产生的输出电压或电流波形。在另一个实施例中，功率接收电路包括用于从调制载波信号恢复数据的模拟电路（610）。去耦装置（630）将模拟电路（610）与负载的阻抗变化隔离。分流装置（640）从负载转移不需要的电流。

2. 发明授权

US6023191A Method and apparatus for detecting an input signal 失效
标题翻译：用于检测输入信号的方法和装置
公开(公告)号：US6023191A
公开(公告)日：2000-02-08
申请号：US920369
申请日：1997-08-29
申请人： Lawrence Edwin Connell , Mark Joseph Callicotte , William Joseph Roeckner
发明人： Lawrence Edwin Connell , Mark Joseph Callicotte , William Joseph Roeckner
IPC分类号： G01R19/00 , H03D1/00 , H03G7/00 , H03G7/08 , H03H19/00 , H03K5/00
CPC分类号： H03G7/007
摘要： A level detector detects an input signal level. A rectifier (210) receives the input signal and provides a rectified signal. A prefilter (220) receives the rectified signal and attenuates high frequency components at frequencies near multiples of a decimation sample rate. The prefiltered signal is decimated (230) and low pass filtered by a lowpass filter (240) having a passband below the input frequency of the input signal. The level detector can be provided to control a variable gain stage circuit (935, 1010) which applies a gain to the input signal based on the level to form a dynamic range compressor or expander.
摘要翻译：电平检测器检测输入信号电平。整流器（210）接收输入信号并提供整流信号。预滤波器（220）接收经整流的信号，并以接近抽取采样率的倍数的频率衰减高频分量。预滤波信号被抽取（230），并且通过具有低于输入信号的输入频率的通带的低通滤波器（240）进行低通滤波。可以提供电平检测器以控制可变增益级电路（935,1010），该可变增益级电路基于该电平对输入信号施加增益以形成动态范围压缩器或扩展器。

3. 发明授权

US06995482B2 Switching circuit and method therefor 失效
标题翻译：开关电路及其方法
公开(公告)号：US06995482B2
公开(公告)日：2006-02-07
申请号：US10828090
申请日：2004-04-20
申请人： Pallab Midya , Cesar Pascual , Lawrence Edwin Connell
发明人： Pallab Midya , Cesar Pascual , Lawrence Edwin Connell
IPC分类号： H02B1/24
CPC分类号： H02M1/32 , H02M7/538 , H02M7/5387 , Y10T307/74 , Y10T307/76 , Y10T307/911 , Y10T307/918
摘要： A method for providing a current path during switching transitions of a switching circuit while limiting the short circuit current. In one embodiment, a switching circuit includes a passive break-before-make element in series with two switches. An alternate embodiment includes a make-before-break element in parallel with the switches. The passive break-before-make element, or make-before-break element, provides a high impedance in a short term and a low impedance in a long term. The switching circuit may be coupled to a load through a low pass filter. In one embodiment, the switching circuit is used in a switching audio amplifier circuit, where correction of nonlinearities incorporates analog feedback to modify the duty ratio of a digitally generated switching signal in the analog domain.
摘要翻译：一种用于在切换电路切换转换期间提供电流路径同时限制短路电流的方法。在一个实施例中，开关电路包括与两个开关串联的被动断开元件。替代实施例包括与开关并联的断开元件。被动断开元件或断开元件在短期内提供高阻抗，并在长期内提供低阻抗。开关电路可以通过低通滤波器耦合到负载。在一个实施例中，切换电路用于开关音频放大器电路中，其中非线性校正包括模拟反馈以修改模拟域中的数字产生的开关信号的占空比。

4. 发明授权

US06750704B1 Offset compensated differential amplifier 有权
标题翻译：偏置补偿差分放大器
公开(公告)号：US06750704B1
公开(公告)日：2004-06-15
申请号：US10340335
申请日：2003-01-09
申请人： Lawrence Edwin Connell , Craig S. Petrie , Matthew R. Miller
发明人： Lawrence Edwin Connell , Craig S. Petrie , Matthew R. Miller
IPC分类号： H03F102
CPC分类号： H03F3/45753 , H03F2200/331
摘要： A differential amplifier comprises a differential input stage including first and second input devices and has first and second input electrodes and first and second output terminals. A differential load stage includes first and second load devices having first and second control electrodes respectively. The load stage is coupled to the differential input stage and to the first and second output terminals. First and second separate capacitive biasing networks are coupled to the first and second output terminals and respectively to the first and second control electrodes. During an offset-cancellation phase, the input electrodes are coupled to a common voltage. During an amplification phase, a differential input signal is applied to the input electrodes.
摘要翻译：差分放大器包括具有第一和第二输入装置的差分输入级，并具有第一和第二输入电极以及第一和第二输出端子。差分负载级包括分别具有第一和第二控制电极的第一和第二负载装置。负载级耦合到差分输入级以及第一和第二输出端。第一和第二分离电容偏置网络耦合到第一和第二输出端子，并分别耦合到第一和第二控制电极。在偏移消除阶段期间，输入电极耦合到公共电压。在放大阶段期间，差分输入信号被施加到输入电极。

5. 发明授权

US06559723B2 Single ended input, differential output amplifier 有权
标题翻译：单端输入，差分输出放大器
公开(公告)号：US06559723B2
公开(公告)日：2003-05-06
申请号：US09946030
申请日：2001-09-04
申请人： Neal W. Hollenbeck , Lawrence Edwin Connell
发明人： Neal W. Hollenbeck , Lawrence Edwin Connell
IPC分类号： H03F304
CPC分类号： H03F3/193
摘要： A single ended input differential output amplifier (100) and integrated circuit including such an amplifier (100). A pair of load resistors (102, 104) are connected between a supply voltage (Vdd) and differential outputs OUTP and OUTM. An inductor (106) is connected between input RFIN and a source bias voltage VBS. A first field effect transistor (FET) (108) is connected, drain to source, between load resistor (102) at output OUTP and inductor (106) at RFIN. A second FET (110) is connected, drain to source, between the second load resistor (104) at output OUTM and the source bias voltage VBS. A gate bias voltage VBg is connected to the gate of FET (108) and through resistor (112) to the gate of FET (110). A coupling capacitor (114) is connected between the input RFIN and the gate of FET (110). The gate of FET (108) may be connected to gate bias voltage VBg through a second gate bias resistor (122) and a second coupling capacitor (124) may couple the source of FET (110) to the gate of FET (108), thereby providing common mode rejection for noise, e.g., substrate noise, experienced at inductor (106).
摘要翻译：单端输入差分输出放大器（100）和包括这种放大器（100）的集成电路。一对负载电阻（102,104）连接在电源电压（Vdd）和差分输出OUTP和OUTM之间。电感器（106）连接在输入RFIN和源极偏置电压VBS之间。第一场效应晶体管（FET）（108）在RFIN处，在输出OUTP处的负载电阻（102）和电感（106）之间以漏极到源极连接。在输出OUTM处的第二负载电阻（104）和源极偏置电压VBS之间，第二FET（110）从漏极到源极连接在第二负载电阻（104）之间。栅极偏置电压VBg连接到FET（108）的栅极并通过电阻（112）连接到FET（110）的栅极。耦合电容器（114）连接在输入RFIN和FET（110）的栅极之间。 FET（108）的栅极可以通过第二栅极偏置电阻器（122）连接到栅极偏置电压VBg，并且第二耦合电容器（124）可以将FET（110）的源极耦合到FET（108）的栅极，从而为电感器（106）所经历的噪声（例如衬底噪声）提供共模抑制。

6. 发明授权

US06441594B1 Low power voltage regulator with improved on-chip noise isolation 有权
标题翻译：低功率稳压器，具有改进的片内噪声隔离
公开(公告)号：US06441594B1
公开(公告)日：2002-08-27
申请号：US09845059
申请日：2001-04-27
申请人： Lawrence Edwin Connell , Daniel Patrick McCarthy
发明人： Lawrence Edwin Connell , Daniel Patrick McCarthy
IPC分类号： G05F140
CPC分类号： G05F1/575
摘要： A voltage regulator 100, 130 for isolating radio frequency circuits from on chip digital circuit originated noise and an integrated circuit chip including the voltage regulator. The voltage regulator 100, 130 includes regulator device (a PFET) 106 driven by a sense amplifier 110 to derive a regulator voltage 108 from a supply voltage 102. Another sense amplifier 114 senses changes in output load and adjusts current flow through a current shunt 120, 122 so that the current shunt 120, 122 shunts excess load current. The sense amplifier 110 driving the voltage regulator device 106 senses current flow through the current shunt 120, 122 and adjusts the current supplied by the regulator device 106 to reduce excess current. The current shunt 120, 122 is a series connected PFET 120 and NFET diode 122, with the gate of the PFET 120 driven to control current flow. Each of the sense amplifiers 110, 114 includes a pair of PFETs 132, 134 140, 142 and a pair of NFETs 136, 138 144, 146, the drain of each PFET of the pair is tied to a corresponding drain of one of the pair of NFETs. A voltage divider 116, 118 connected between the regulator voltage 108 and ground provides a sense voltage to the output sense amplifier 114 so that the output sense amplifier compares the sense voltage against a reference voltage (VREF) to determine whether the regulator device is providing too much, not enough or just the right output current level.
摘要翻译：用于将射频电路与片上数字电路产生的噪声隔离的电压调节器100,130和包括电压调节器的集成电路芯片。电压调节器100,130包括由读出放大器110驱动以从电源电压102导出调节器电压108的调节器装置（PFET）106。另一个读出放大器114感测输出负载的变化并调节通过电流分流器120的电流，122，使得电流分流器120,122分流多余的负载电流。驱动电压调节器装置106的读出放大器110感测通过电流分流器120,122的电流，并且调节由调节器装置106提供的电流以减少过电流。电流分流器120,122是串联连接的PFET 120和NFET二极管122，PFET 120的栅极被驱动以控制电流。读出放大器110,114中的每一个包括一对PFET 132,134 140,142和一对NFET 136,138,144,146，该对的每个PFET的漏极被连接到该对中的一个的相应漏极的NFET。连接在调节器电压108和地之间的分压器116,118向输出读出放大器114提供感测电压，使得输出读出放大器将感测电压与参考电压（VREF）进行比较，以确定调节器装置是否也提供很多，不够或只是正确的输出电流水平。

7. 发明授权

US06920316B2 High performance integrated circuit regulator with substrate transient suppression 有权
标题翻译：具有基板瞬态抑制的高性能集成电路调节器
公开(公告)号：US06920316B2
公开(公告)日：2005-07-19
申请号：US09946010
申请日：2001-09-04
申请人： Lawrence Edwin Connell , Neal W. Hollenbeck , Michael Lee Bushman , Daniel Patrick McCarthy
发明人： Lawrence Edwin Connell , Neal W. Hollenbeck , Michael Lee Bushman , Daniel Patrick McCarthy
IPC分类号： H03K19/003 , G05F1/56 , H03K3/356 , H03L7/08 , H03L7/089 , H03L7/18 , H04B1/26 , H04B1/18
CPC分类号： G05F1/56 , H03L7/0891 , H03L7/18
摘要： A regulation circuit, incorporated in a single integrated circuit with a first circuit load, which as an input coupled to a power supply which produces a source voltage, and a first output coupled to the first circuit load. The regulation circuit comprises an input capacitor for reducing the magnitude of a voltage change at the first output, and at least a first voltage regulator for producing a predetermined voltage at the first load.
摘要翻译：一种调节电路，其结合在具有第一电路负载的单个集成电路中，其作为耦合到产生源极电压的电源的输入以及耦合到第一电路负载的第一输出。调节电路包括用于减小第一输出处的电压变化幅度的输入电容器和至少第一电压调节器，用于在第一负载下产生预定电压。

8. 发明授权

US5708595A Efficient median filter and method therefor 失效
标题翻译：高效中值滤波器及其方法
公开(公告)号：US5708595A
公开(公告)日：1998-01-13
申请号：US398340
申请日：1995-03-03
申请人： Lawrence Edwin Connell
发明人： Lawrence Edwin Connell
IPC分类号： G06F7/02 , G06F17/18 , H03H17/00 , H03H17/02 , G06F7/00
CPC分类号： H03H17/0263 , G06F17/18
摘要： An efficient method and apparatus of median filtering includes a memory circuit (305) for holding a list of N data samples (109). A grading circuit (309, 321, 313, 311) identifies a first data sample of the N data samples that has a first metric with a magnitude less than or equal to (N-1)/2, and a second metric with a magnitude greater than or equal to (N-1)/2. The first metric is indicative of a quantity of data samples, exclusive of the first data sample, that have a magnitude less than a magnitude of the first data sample. The second metric is indicative of a quantity of data samples, exclusive of the first data sample, that have a magnitude less than or equal to the magnitude of the first data sample.
摘要翻译：中值滤波的有效方法和装置包括用于保存N个数据采样列表（109）的存储器电路（305）。分级电路（309,321,313,311）识别具有幅度小于或等于（N-1）/ 2的第一度量的N个数据采样的第一数据样本，以及具有幅度的第二度量大于或等于（N-1）/ 2。第一度量表示除了第一数据样本之外的具有小于第一数据样本量值的数据量的数据样本数量。第二度量指示具有小于或等于第一数据样本的幅度的幅度的数据样本量，排除第一数据样本。

9. 发明授权

US5905393A Unbuffered latch resistant to back-writing and method of operation therefor 失效
标题翻译：无缓冲锁扣，可逆写入及其操作方法
公开(公告)号：US5905393A
公开(公告)日：1999-05-18
申请号：US944777
申请日：1997-10-06
申请人： William John Rinderknecht , Lawrence Edwin Connell
发明人： William John Rinderknecht , Lawrence Edwin Connell
IPC分类号： H03K3/356
CPC分类号： H03K3/356121
摘要： An unbuffered flip-flop includes feedback control circuitry providing adaptive control of the internal node during the transfer and latching phases of the flip-flop to prevent back-writing. A complementary pair of transmission gates controlled by the output node are included in the feedback path between an output buffer and a feedback buffer. As noise voltage variations and spikes alter the voltage on the output node, the charge transmittance of the transmission gates is weakened or shut off, thereby preventing the incorrect logic state from being driven by the feedback buffer through to the input of the flip-flop's output buffer and causing back writing. Because the transmission gate transistors are complementary, one transistor or the other will be operating in a transmissive state for each of the bi-stable states of the output buffer during static operation of the flip-flop. As will be appreciated, because only two extra transistors are needed, the present invention has improved performance while consuming very little silicon area, power, and adding almost no delay to the circuit.
摘要翻译：无缓冲触发器包括反馈控制电路，其在触发器的传送和锁存阶段期间提供对内部节点的自适应控制，以防止反写入。由输出节点控制的互补传输门对被包括在输出缓冲器和反馈缓冲器之间的反馈路径中。随着噪声电压变化和尖峰改变输出节点上的电压，传输门的电荷透过率被削弱或切断，从而防止错误的逻辑状态被反馈缓冲器驱动到触发器输出的输入端缓冲并导致回写。由于传输栅极晶体管是互补的，所以在触发器的静态操作期间，一个晶体管或另一个晶体管将在输出缓冲器的每个双稳态状态下以透射状态工作。如将理解的，由于仅需要两个额外的晶体管，本发明在消耗非常少的硅面积，功率并且几乎不向电路添加延迟的同时具有改进的性能。

10. 发明授权

US5875197A Addressable serial test system 失效
标题翻译：可寻址串口测试系统
公开(公告)号：US5875197A
公开(公告)日：1999-02-23
申请号：US441560
申请日：1995-05-15
申请人： Lawrence Edwin Connell
发明人： Lawrence Edwin Connell
IPC分类号： G01R31/28 , G01R31/3185 , G01K31/28
CPC分类号： G01R31/318558
摘要： An addressable serial test system employs a serial register with parallel outputs. Data is clocked into the serial register via a shift clock signal. A decoder is connected to a portion of the shift register's outputs and provides a selection signal dependent on the data clocked into the serial register. A system clock generates a system clock signal. A storage element includes a clock input coupled to the system clock signal, a data input, an output, a load input coupled to the selection signal, and a test data input coupled to another portion of the shift register's outputs. The storage element's output is alternately forced to a state indicative of the test data input by the selection signal and forced to a state indicative of the data input by the system clock. Structure is included to configure the serial register to read the contents of the storage element.
摘要翻译：可寻址串行测试系统采用具有并行输出的串行寄存器。数据通过移位时钟信号输入串行寄存器。解码器连接到移位寄存器输出的一部分，并提供取决于定时进入串行寄存器的数据的选择信号。系统时钟产生系统时钟信号。存储元件包括耦合到系统时钟信号的时钟输入，数据输入，输出，耦合到选择信号的负载输入以及耦合到移位寄存器的输出的另一部分的测试数据输入。存储元件的输出被交替地强制为指示由选择信号输入的测试数据的状态，并被强制为指示由系统时钟输入的数据的状态。包括结构以配置串行寄存器来读取存储元件的内容。

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