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    • 2. 发明授权
    • Simultaneous vision emulation for fitting of corrective multifocal contact lenses
    • 用于矫正多焦点隐形眼镜的同时视觉仿真
    • US07455403B2
    • 2008-11-25
    • US11463053
    • 2006-08-08
    • Larry G. JonesJohn R. Buch
    • Larry G. JonesJohn R. Buch
    • G02C7/04A61B3/10
    • A61B3/0285A61B3/04
    • An emulator including a beam splitter for splitting incoming light energy into a first component directed along a first optical path, and a second component directed along a second optical path distinct from the first optical path. The emulator includes a first receptacle positioned to pass light energy directed along only the first optical path. The first receptacle is capable of receiving an add lens for providing an add power. A beam combiner is positioned to combine light energy of the second component with light energy of the first component that has passed the first receptacle, i.e. to have the add power applied, and to direct the combined light energy along a common optical path. Additional receptacles are provided that are capable of receiving a sphere and/or a cylindrical lens in position to pass the combined light energy traveling along the common optical path.
    • 一种仿真器,包括用于将入射光能分解成沿着第一光路指向的第一分量的分束器,以及沿着与第一光路不同的第二光路指向的第二分量。 仿真器包括第一插座,其被定位成传递仅沿着第一光路指向的光能。 第一容器能够接收用于提供附加功率的附加镜头。 光束组合器被定位成将第二部件的光能与已经通过第一插座的第一部件的光能组合,即具有施加的附加功率,并沿着公共光路引导组合的光能。 提供了附加的插座,其能够接收球体和/或柱面透镜在适当位置以通过沿着公共光路行进的组合光能量。
    • 8. 发明授权
    • Logic gate size optimization process for an integrated circuit whereby
circuit speed is improved while circuit area is optimized
    • 用于集成电路的逻辑门尺寸优化处理,从而在优化电路面积的同时提高电路速度
    • US5619418A
    • 1997-04-08
    • US390210
    • 1995-02-16
    • David T. BlaauwJoseph W. NortonLarry G. JonesSusanta MisraR. Iris Bahar
    • David T. BlaauwJoseph W. NortonLarry G. JonesSusanta MisraR. Iris Bahar
    • G06F17/50
    • G06F17/505
    • An integrated circuit, when designed, must adhere to timing constraints while attempting to minimize circuit area. In order to adhere to timing specifications while arriving at a near-optimal circuit surface area, an iterative process is used which selectively increases logic gates sizes by accessing logic gates from a memory stored logic gate library. A circuit representation is read along with timing constraints for circuit paths. Each circuit path in the circuit is processed to find it's actual circuit path delay. A most out-of-specification circuit path (in terms of speed) is chosen in the circuit and a sensitivity calculation is performed for each logic gate in the most out-of-specification circuit path. The logic gate in the circuit path with the maximized sensitivity (sensitivity=.DELTA.speed/.DELTA.area) is increased in size by accessing a larger gate in the library in order to improve speed at the expense of area. The above process continues iteratively until no out-of-specification circuit paths are found.
    • 集成电路在设计时必须遵守时序约束,同时尽量减少电路面积。 为了在达到近似最佳电路表面积的同时遵循定时规范,使用迭代过程,其通过从存储器存储逻辑门库访问逻辑门来选择性地增加逻辑门大小。 电路表示与电路路径的时序约束一起读取。 处理电路中的每个电路路径以找到其实际的电路路径延迟。 在电路中选择最不符合规范的电路路径(在速度方面),并且在最规范的电路路径中对每个逻辑门执行灵敏度计算。 具有最大灵敏度(灵敏度= DELTA速度/ DELTA面积)的电路路径中的逻辑门的大小通过访问库中较大的门而增加,以便以面积为代价来提高速度。 上述过程继续进行,直到找不到超出规范的电路路径。
    • 10. 发明授权
    • Speeding up timing analysis by reusing delays computed for isomorphic subcircuits
    • 通过重新使用同构子电路计算的延迟来加快时序分析
    • US07451412B2
    • 2008-11-11
    • US11198451
    • 2005-08-04
    • Larry G. JonesFeng LiMohan Rangan GovindarajBradley R. RoetcisoenderMichael G. Weaver
    • Larry G. JonesFeng LiMohan Rangan GovindarajBradley R. RoetcisoenderMichael G. Weaver
    • G06F17/50
    • G06F17/5031
    • One embodiment of the present invention provides a system that speeds up timing analysis by reusing delays computed for isomorphic subcircuit. During operation, the system receives a circuit block to be analyzed, wherein the circuit block is in the form of a netlist. The system then subdivides the circuit block into a set of subcircuits. The subcircuits are then partitioned into equivalence classes, which contain subcircuits which are topologically isomorphic to each other. Next, the system performs a timing analysis by tracing paths through a timing graph for the circuit block. During this timing analysis, whenever a delay is required for a subcircuit, the system determines if a corresponding delay has been already computed for the equivalence class associated with the subcircuit. If so, the system reuses the delay. If not, the system computes the delay for the subcircuit, and then associates the computed delay with the equivalence class so that the computed delay can be reused for isomorphic subcircuits.
    • 本发明的一个实施例提供了一种系统,其通过重新利用为同构子电路计算的延迟来加速时序分析。 在操作期间,系统接收要分析的电路块,其中电路块是网表的形式。 然后,系统将电路块细分成一组子电路。 然后将子电路分成等价类,其中包含彼此拓扑上同构的子电路。 接下来,系统通过用于电路块的时序图跟踪路径来执行定时分析。 在此定时分析期间,每当子电路需要延迟时,系统确定是否已经为与子电路相关联的等效类计算了相应的延迟。 如果是这样,系统重新使用延迟。 如果不是,则系统计算子电路的延迟,然后将计算的延迟与等价类相关联,使得计算的延迟可以重用于同构子电路。